43results about How to "Guaranteed Electrical Characteristics" patented technology

A pickup device employing an inexpensive flexible printed circuit sheet (FPC) which demonstrates preferable electrical characteristics. FPC has a signal conductive layer inside, and a U-shape bending portion is formed in a midway of FPC at a position where a hologram unit is connected. An opening is formed on FPC adjacent to an area when the hologram unit is connected, and the length of this opening is longer than the height of the hologram unit.

An elastic wave device includes a piezoelectric substrate, an IDT electrode disposed on the piezoelectric substrate, a wiring electrode disposed on the piezoelectric substrate and connected to the IDT electrode, a first insulator disposed on the piezoelectric substrate to seal the IDT electrode and the wiring electrode, a resin layer provided on the first insulator, an inductor electrode disposed on the resin layer, a second insulator disposed on the resin layer to cover the inductor electrode, a terminal electrode disposed on the second insulator, and a connecting electrode passing through the first insulator, the second insulator, and the resin layer to electrically connect the wiring electrode, the terminal electrode, and the inductor electrode. The first insulator includes a resin and filler dispersed in the resin. A density of filler in the resin layer is smaller than an average density of the filler in the first insulator. This elastic wave device has excellent characteristics of the inductor while reducing variations of the characteristics.

Embodiments of the present invention provide a display backplane, a manufacturing method thereof, and a display device. The display backplane includes: a base, a transparent heat conduction layer disposed on the base, and an array structure layer disposed on the heat conduction layer; the array structure layer includes a light-shielding layer, a first thin film transistor, and a second thin film transistor, so The light-shielding layer is arranged between the transparent thermal conduction layer and the first thin film transistor. The transparent heat conduction layer includes a transparent conductive layer, a transparent semiconductor layer, or a transparent conductive layer and a transparent semiconductor layer. The present invention can effectively solve the problem of separation of characteristics of the driving thin film transistor and the switching thin film transistor existing in the existing OLED display device by disposing the transparent heat conduction layer between the base and the array structure layer.

The invention provides a method for forming a semiconductor-device replacement gate and a method for manufacturing the semiconductor device. The method includes: providing a semiconductor substrate which includes an N-type area and a P-type area; forming a sacrifice-gate stack on each of the N-type area and the P-type area respectively, wherein each sacrifice-gate stack includes a sacrifice-gate dielectric and a sacrifice-gate electrode, the sacrifice-gate electrode is located on the sacrifice-gate dielectric and the sacrifice-gate electrode in the N-type area is higher than the gate electrode of the P-type area; forming a side wall around each sacrifice-gate stack; forming source-drain areas on the semiconductor substrate at the two sides of the sacrifice-gate stacks; removing the sacrifice-gate stack in the N-type area so as to form a first opening in the side wall; and forming an N-type replacement-gate stack in the first opening; removing the sacrifice-gate stack in the P-type area so as to form a second opening; forming a P-type replacement-gate stack in the second opening; and performing planarization until the N-type replacement-gate stack is exposed. The method is simple in process.

The invention discloses a preparation method of a heat shock-resistant ceramic capacitor and pertains to the field of electric elements and material technology, in particular to a preparation method of a ceramic capacitor; the preparation method comprises the steps: the preparation of transition electrodes is added into the conventional ceramic-capacitor preparation engineering; single-layer or multi-layer transition electrodes with different silver contents are prepared at two sides of a ceramic chip; due to the different silver contents in the transition electrodes and electrode materials, the thermal conductivities of the transition electrodes and electrode materials are different; therefore, thermal gradient exists between the transition electrodes, which can relieve the thermal stress produced by the synergy of the ceramic capacitor in an environment in which the temperature changes dramatically. On the basis of ensuring electrical characteristics of the ceramic capacitor, the preparation method significantly improves the heat shock resistance of the ceramic capacitor so that the ceramic capacitor can adapt to the environment in which the temperature changes between minus 55 DEG C to 125 DEG C and particularly meets the performance requirements of a special ceramic capacitor in automotive electronics.

The invention discloses a method for saving the area of a medium- and low-voltage VDMOSFET chip. Electrical properties of a VDMOS device can be guaranteed, and manufacturing cost is minimized. The method comprises the following steps: firstly, an active region (1a) and a non-corrosive region (1b) are formed on polycrystalline silicon through corrosion; a polycrystalline silicon region (2) is formed on the active region (1a) through deposition, and the polycrystalline silicon region (2) contains a polycrystalline silicon lead region (2a) and a polycrystalline silicon terminal structural region (2b); N+source regions (3) are formed below the polycrystalline silicon lead region (2a) and below the space between the polycrystalline silicon lead region (2a) and the polycrystalline silicon terminal structural region (2b) through diffusion; contact holes (4) are formed on the polycrystalline silicon region; a metal electrode (5) is formed on the active region (1a); the metal electrode (5) extends to cover all the contact holes (4); the contact holes (4) are connected to the N+source regions (3) through the metal electrode (5); and the metal electrode (5) and part of the polycrystalline silicon terminal structural region (2b) are overlapped.