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43results about How to "Guaranteed Electrical Characteristics" patented technology

Unsealing method for flip chip device

The invention discloses an unsealing method for a flip chip device. The method comprises the steps that a three-dimensional microscope is used for observing a device to be unsealed, and the appearance size, packaging thickness, packaging forms and packaging materials of the device to be unsealed are measured; one or more of a scanning acoustic microscope, a micro-focus X ray detector and a CT detector are selected to observe and record the device to be unsealed; the unsealing scheme of the device is determined according to the type of the device and the detecting results; embedding polishing or shell unsealing is used for carrying out unsealing pre-processing on the device to be unsealed; one or more of a mask etching method, a chemical etching method and a section microscopy method are used for carrying out chemical unsealing on the device to be unsealed; the interior technical parameters of the unsealed device are detected, evaluated and analyzed. Compared with a traditional unsealing method for a flip chip technology device, the unsealing method for the flip chip device has the advantages that the unsealing quality is greatly improved, and completeness and electrical characteristics of an unsealed silicon wafer are guaranteed.
Owner:CASIC DEFENSE TECH RES & TEST CENT

Small electrical planar huyghens source antenna

The invention discloses a small electrical planar huyghens source antenna. The small electrical planar huyghens source antenna comprises an upper-layer dielectric substrate, a lower-layer dielectric substrate, an electric dipole, a magnetic dipole, a first excitation strip, a second excitation strip and a coaxial cable, wherein the upper-layer dielectric substrate and the lower-layer dielectric substrate are laminated, the electric substrate is in contact with an upper surface of the upper-layer dielectric substrate, the magnetic dipole is in contact with a lower surface of the lower-layer dielectric substrate, the first excitation strip and the second excitation strip are arranged between the upper-layer dielectric substrate and the lower-layer dielectric substrate, the coaxial cable comprises an inner conductor and an outer conductor, the inner conductor passes through the lower-layer dielectric substrate to be connected with the first excitation strip, and the outer conductor passes through the lower-layer dielectric substrate to be connected with the second excitation strip. Through the abovementioned technical scheme, on one hand, the small electrical huyghens source antenna with a single feeding source is achieved by organically combining the electric dipole and the magnetic dipole by means of a near-field coupling resonant technology; and on the other hand, the huyghens source antenna directly adopts non-balance feeding, namely the single coaxial cable feeds, and other auxiliary feeding structures such as a Balun and a power divider are not needed.
Owner:CHONGQING UNIV +1

Method for forming semiconductor-device replacement gate and method for manufacturing semiconductor device

The invention provides a method for forming a semiconductor-device replacement gate and a method for manufacturing the semiconductor device. The method includes: providing a semiconductor substrate which includes an N-type area and a P-type area; forming a sacrifice-gate stack on each of the N-type area and the P-type area respectively, wherein each sacrifice-gate stack includes a sacrifice-gate dielectric and a sacrifice-gate electrode, the sacrifice-gate electrode is located on the sacrifice-gate dielectric and the sacrifice-gate electrode in the N-type area is higher than the gate electrode of the P-type area; forming a side wall around each sacrifice-gate stack; forming source-drain areas on the semiconductor substrate at the two sides of the sacrifice-gate stacks; removing the sacrifice-gate stack in the N-type area so as to form a first opening in the side wall; and forming an N-type replacement-gate stack in the first opening; removing the sacrifice-gate stack in the P-type area so as to form a second opening; forming a P-type replacement-gate stack in the second opening; and performing planarization until the N-type replacement-gate stack is exposed. The method is simple in process.
Owner:INST OF MICROELECTRONICS CHINESE ACAD OF SCI

Preparation method of low-thermal-resistance gallium nitride high-electron-mobility transistor epitaxial material

The invention discloses a preparation method of a low-thermal-resistance gallium nitride high-electron-mobility transistor epitaxial material, and belongs to the technical field of semiconductor epitaxial materials. According to the invention, the method comprises the steps: employing high-temperature chemical vapor deposition equipment for carrying out high-temperature etching on the surface of a silicon carbide substrate, so the surface of the substrate presents controllable atomic-scale step morphology; carrying out the atomic-scale aluminum nitride nucleation on silicon carbide atomic steps by utilizing a metal organic chemical vapor deposition technology; transversely and rapidly combining the aluminum nitride nucleation points in an intermittent source supply mode, and performing layered deposition, so high-quality nanoscale aluminum nitride nucleation layer growth is achieved, and the gallium nitride high-electron-mobility transistor is prepared by taking aluminum nitride as a substrate. According to the method, the thickness of the aluminum nitride nucleating layer can be greatly reduced, the interface thermal resistance introduced by the aluminum nitride nucleating layer can be effectively reduced, the heat dissipation characteristic of the gallium nitride power device can be improved, and the method has extremely important significance for improving the power performance of the gallium nitride microwave power device.
Owner:NO 55 INST CHINA ELECTRONIC SCI & TECHNOLOGYGROUP CO LTD

Power module and vehicle with same

The invention discloses a power module and a vehicle with the same. The power module comprises a shell, a power chip, a first heat radiation substrate and a second heat radiation substrate. An accommodation cavity is defined in the shell and is filled with insulation material. The first heat radiation substrate and the second heat radiation substrate are oppositely arranged. The power chip, the first heat radiation substrate and the second heat radiation substrate are all positioned in the accommodation cavity and are covered by the insulation material. The first heat radiation substrate and the second heat radiation substrate are arranged on the upper surface and the lower surface of the power chip respectively. A collector electrode is led out of the second heat radiation substrate, an emitting electrode is led out of the first heat radiation substrate, and a gate electrode is led out of the power chip. According to the power module provided by the embodiment of the invention, the upper and lower surfaces of the power chip achieve heat radiation at the same time, so that the heat radiation performance of the power module is greatly enhanced, thereby improving the reliability of the power module, and by arranging the insulation material in the shell, the effect of electrical insulation is achieved, devices in the shell are prevented from interference, and independent electrical features of each device are ensured.
Owner:BYD SEMICON CO LTD

Array substrate, backlight module, display panel, display device and preparation method

The embodiment of the invention discloses an array substrate, a backlight module, a display panel, a display device and a preparation method. The array substrate comprises a plurality of driving units. Each driving unit comprises a first electrode, a second electrode and at least one thin film transistor; the first electrode and the second electrode are used for being connected with the anode andthe cathode of a light emitting diode respectively, so that the vertical projection of the light emitting diode on the array substrate can be overlapped with the at least one thin film transistor, andthe thin film transistor is located at the backlight side of the light emitting diode in the light emitting direction of the light emitting diode. The driving unit controls the light-emitting diode to be turned on or off according to the driving signal. According to the embodiment of the invention, the problem that an existing array substrate needs to be additionally provided with a shading layer, so that the preparation process is complex, is solved; the influence of external illumination on the thin film transistor can be avoided, masks and preparation procedures required for preparing theshading layer are saved, the preparation process of the array substrate is simplified, and the manufacturing cost is reduced.
Owner:SHANGHAI TIANMA MICRO ELECTRONICS CO LTD

Method for saving area of medium- and low-voltage VDMOSFET chip

The invention discloses a method for saving the area of a medium- and low-voltage VDMOSFET chip. Electrical properties of a VDMOS device can be guaranteed, and manufacturing cost is minimized. The method comprises the following steps: firstly, an active region (1a) and a non-corrosive region (1b) are formed on polycrystalline silicon through corrosion; a polycrystalline silicon region (2) is formed on the active region (1a) through deposition, and the polycrystalline silicon region (2) contains a polycrystalline silicon lead region (2a) and a polycrystalline silicon terminal structural region (2b); N+source regions (3) are formed below the polycrystalline silicon lead region (2a) and below the space between the polycrystalline silicon lead region (2a) and the polycrystalline silicon terminal structural region (2b) through diffusion; contact holes (4) are formed on the polycrystalline silicon region; a metal electrode (5) is formed on the active region (1a); the metal electrode (5) extends to cover all the contact holes (4); the contact holes (4) are connected to the N+source regions (3) through the metal electrode (5); and the metal electrode (5) and part of the polycrystalline silicon terminal structural region (2b) are overlapped.
Owner:BEIJING MXTRONICS CORP +1

Medium-low voltage switch cabinet and servomotor drive mechanism thereof

InactiveCN108736324AAvoid failures such as heating and burning switchesSave the process of debugging and testingBoards/switchyards circuit arrangementsAC motor controlLow voltageEngineering
The invention relates to a medium-low voltage switch cabinet and a servomotor drive mechanism thereof. The medium-low voltage switch cabinet specifically comprises a circuit breaker servomotor, a three-position switch servomotor and a PWM driver, wherein each moving contact of a circuit breaker is connected with a main shaft of the circuit breaker servomotor through a circuit breaker drive mechanism; the moving contact of a three-position switch is connected with the main shaft of the three-position switch servomotor through a three-position switch drive mechanism; and the PWM driver is in control connection with the circuit breaker servomotor and the three-position switch servomotor. According to the medium-low voltage switch cabinet, a motor mechanism is applied to a C-GIS product to replace a spring mechanism of a traditional circuit breaker, so that mechanical movement faults, such as incomplete closing and excessive closing force of traditional equipment are avoided; the faults, such as switch burnout caused by heating of the contacts of a conductive system are avoided; and meanwhile, the time-consuming and labor-intensive debugging and testing processes of the traditional equipment are also saved.
Owner:PINGGAO GRP +1

Flexible anti-aging shielding twisted pair cable and preparation method thereof

The invention discloses a flexible anti-aging shielding twisted pair cable and a preparation method thereof. The cable is characterized in that four twisted-pair wire cores and a cross-shaped fillingcore material are twisted together to form a cable core, the exterior of the cable core is coated with a fluororesin wrapping tape layer, an aluminum-plastic composite tape wrapping layer, a copper wire shielding winding layer and a silane grafted crosslinked high-density polyethylene insulating layer, the pair-twisted wire core is formed by pair twisting of two insulating wire cores, each insulating wire core comprises an inner conductor and a silane grafted crosslinked low-density polyethylene insulating layer, a nickel copper damage prevention coating and a zinc oxide barrier layer are sequentially sprayed outside the inner conductor and the copper wire shielding winding layer, the cross-shaped filling core material comprises a cross-shaped resin matrix and an aluminum foil layer, an aluminum-plastic composite belt wrapping layer is of an aluminum-plastic composite belt gap wrapping structure, and the aluminum-plastic composite belt comprises an aluminum foil belt outer layer and aPET resin belt inner layer. The cable is advantaged in that the cable effectively suppresses signal interference caused by crosstalk between the pair-twisted wire cores, can effectively suppress a copper damage phenomenon of an insulating layer, and has better mechanical strength, flexibility and electrical characteristics.
Owner:浙江元通线缆制造有限公司

Method for preparing heat impact resisting ceramic capacitor

ActiveCN101494116AImproved thermal shock resistanceSolve thermal stressFixed capacitor electrodesThermal conductivityMetallurgy
The invention discloses a preparation method of a heat shock-resistant ceramic capacitor and pertains to the field of electric elements and material technology, in particular to a preparation method of a ceramic capacitor; the preparation method comprises the steps: the preparation of transition electrodes is added into the conventional ceramic-capacitor preparation engineering; single-layer or multi-layer transition electrodes with different silver contents are prepared at two sides of a ceramic chip; due to the different silver contents in the transition electrodes and electrode materials, the thermal conductivities of the transition electrodes and electrode materials are different; therefore, thermal gradient exists between the transition electrodes, which can relieve the thermal stress produced by the synergy of the ceramic capacitor in an environment in which the temperature changes dramatically. On the basis of ensuring electrical characteristics of the ceramic capacitor, the preparation method significantly improves the heat shock resistance of the ceramic capacitor so that the ceramic capacitor can adapt to the environment in which the temperature changes between minus 55 DEG C to 125 DEG C and particularly meets the performance requirements of a special ceramic capacitor in automotive electronics.
Owner:CHENGDU HONGMING & UESTC NEW MATERIALS

Method of forming replacement gate of semiconductor device and method of manufacturing semiconductor device

The invention provides a method for forming a semiconductor-device replacement gate and a method for manufacturing the semiconductor device. The method includes: providing a semiconductor substrate which includes an N-type area and a P-type area; forming a sacrifice-gate stack on each of the N-type area and the P-type area respectively, wherein each sacrifice-gate stack includes a sacrifice-gate dielectric and a sacrifice-gate electrode, the sacrifice-gate electrode is located on the sacrifice-gate dielectric and the sacrifice-gate electrode in the N-type area is higher than the gate electrode of the P-type area; forming a side wall around each sacrifice-gate stack; forming source-drain areas on the semiconductor substrate at the two sides of the sacrifice-gate stacks; removing the sacrifice-gate stack in the N-type area so as to form a first opening in the side wall; and forming an N-type replacement-gate stack in the first opening; removing the sacrifice-gate stack in the P-type area so as to form a second opening; forming a P-type replacement-gate stack in the second opening; and performing planarization until the N-type replacement-gate stack is exposed. The method is simple in process.
Owner:INST OF MICROELECTRONICS CHINESE ACAD OF SCI

Method for preparing heat impact resisting ceramic capacitor

The invention discloses a preparation method of a heat shock-resistant ceramic capacitor and pertains to the field of electric elements and material technology, in particular to a preparation method of a ceramic capacitor; the preparation method comprises the steps: the preparation of transition electrodes is added into the conventional ceramic-capacitor preparation engineering; single-layer or multi-layer transition electrodes with different silver contents are prepared at two sides of a ceramic chip; due to the different silver contents in the transition electrodes and electrode materials, the thermal conductivities of the transition electrodes and electrode materials are different; therefore, thermal gradient exists between the transition electrodes, which can relieve the thermal stress produced by the synergy of the ceramic capacitor in an environment in which the temperature changes dramatically. On the basis of ensuring electrical characteristics of the ceramic capacitor, the preparation method significantly improves the heat shock resistance of the ceramic capacitor so that the ceramic capacitor can adapt to the environment in which the temperature changes between minus 55 DEG C to 125 DEG C and particularly meets the performance requirements of a special ceramic capacitor in automotive electronics.
Owner:CHENGDU HONGMING & UESTC NEW MATERIALS

A Method of Saving Vdmosfet Chip Area in Low and Medium Voltage

The invention discloses a method for saving the area of a medium- and low-voltage VDMOSFET chip. Electrical properties of a VDMOS device can be guaranteed, and manufacturing cost is minimized. The method comprises the following steps: firstly, an active region (1a) and a non-corrosive region (1b) are formed on polycrystalline silicon through corrosion; a polycrystalline silicon region (2) is formed on the active region (1a) through deposition, and the polycrystalline silicon region (2) contains a polycrystalline silicon lead region (2a) and a polycrystalline silicon terminal structural region (2b); N+source regions (3) are formed below the polycrystalline silicon lead region (2a) and below the space between the polycrystalline silicon lead region (2a) and the polycrystalline silicon terminal structural region (2b) through diffusion; contact holes (4) are formed on the polycrystalline silicon region; a metal electrode (5) is formed on the active region (1a); the metal electrode (5) extends to cover all the contact holes (4); the contact holes (4) are connected to the N+source regions (3) through the metal electrode (5); and the metal electrode (5) and part of the polycrystalline silicon terminal structural region (2b) are overlapped.
Owner:BEIJING MXTRONICS CORP +1
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