Method of forming replacement gate of semiconductor device and method of manufacturing semiconductor device

Abstract

The invention provides a method for forming a semiconductor-device replacement gate and a method for manufacturing the semiconductor device. The method includes: providing a semiconductor substrate which includes an N-type area and a P-type area; forming a sacrifice-gate stack on each of the N-type area and the P-type area respectively, wherein each sacrifice-gate stack includes a sacrifice-gate dielectric and a sacrifice-gate electrode, the sacrifice-gate electrode is located on the sacrifice-gate dielectric and the sacrifice-gate electrode in the N-type area is higher than the gate electrode of the P-type area; forming a side wall around each sacrifice-gate stack; forming source-drain areas on the semiconductor substrate at the two sides of the sacrifice-gate stacks; removing the sacrifice-gate stack in the N-type area so as to form a first opening in the side wall; and forming an N-type replacement-gate stack in the first opening; removing the sacrifice-gate stack in the P-type area so as to form a second opening; forming a P-type replacement-gate stack in the second opening; and performing planarization until the N-type replacement-gate stack is exposed. The method is simple in process.

Description

technical field [0001] The invention relates to the technical field of ultra-deep submicron semiconductor devices, in particular to a method for forming a replacement gate of a semiconductor device and a method for manufacturing a semiconductor device. Background technique [0002] For more than 40 years, integrated circuits have continued to develop according to Moore's law, with continuous shrinking of feature size, continuous improvement of integration, and increasingly powerful functions. Currently, the feature size of metal-oxide-semiconductor transistors (MOSFETs) has entered sub-50 nanometers. With the continuous reduction of device feature size, if the traditional polysilicon gate is still used, the polysilicon depletion effect will become more and more serious, the polysilicon resistance will also increase, and the boron penetration phenomenon of PMOS will be more significant. These obstacles will Seriously limit the further improvement of device performance. In o...

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Problems solved by technology

However, this method has some insurmountable disadvantages: first, the metal gate electrode is easily penetrated by ions implanted into the source / drain electrode and affects the electrical characteristics of the device; The work function of most metal gate materials will move to the center of the forbidden band after high temperature annealing treatment, resulting in the degradation of device performance

The advantage of this gate-last process is that the metal gate electrode is formed after the high-temperature annealing process for source / drain activation, which avoids the influence of the high-temperature process on the characteristics of the metal gate, enables the device to obtain high stability and consistency, and is conducive to the formation of high-temperature High-k gate dielectric-metal gate semiconductor devices and circuits with high performance; however, the traditional gate-last process is to planarize and remove the dummy gate structure of the N-type device region and the P-type device region at the same time. When using different replacement gate structures, this The process will be very complicated

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