Static random access memory

Abstract

A static random access memory (SRAM) cell includes first through fourth source diffusion regions sequentially arranged in a first direction, a first pass-gate transistor, a source region of which is formed by the first source diffusion region, first and second pull-up transistors, source regions of which are formed by the second source diffusion region, first and second pull-down transistors, source regions of which are formed by the third source diffusion region, a second pass-gate transistor, a source region of which is formed by the fourth source diffusion region, and an intermediate region between the first and second pass-gate transistors linearly extending along a direction parallel to the first direction and across the entire SRAM cell. Each of the first source diffusion region and the fourth source diffusion region is spaced-apart from the intermediate region.

Description

technical field [0001] The present disclosure relates to the layout of SRAM, and more specifically, to the layout of SRAM that can reduce the size of memory cells. Background technique [0002] Generally, when a static random access memory (SRAM) is used for data storage, it is necessary to supply power to the SRAM. To meet the requirements for portable electronic devices and high-speed computing, it is necessary to integrate a considerable number of data storage units into a single SRAM chip, and it may also be necessary to replace conventional transistors with smaller size and lower power consumption vertical transistors to reduce their power consumption. However, integrating vertical transistors into SRAM chips has presented challenges in the semiconductor industry. Contents of the invention [0003] According to some aspects of the present disclosure, a static random access memory (static random access memory; SRAM) storage unit includes a first source diffusion regi...

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Problems solved by technology

However, in the semiconductor industry, integrating vert

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