Serial interface universal verification platform and method based on SV language

Abstract

The invention discloses a serial interface universal verification platform and method based on an SV language. The platform comprises a test excitation signal configuration module, a randomization module, a bottom function module, a driving module, a monitoring and collecting module and a comparison module. The method comprises the following steps that a test excitation signal is configured; randomization operation is conducted on the test excitation signal; a bottom function is called to carry out related operation on a serial interface on a DUT bus; output data of a DUT in the testing process is collected; the output data of the DUT in the testing process and excitation signal data obtained after randomization operation are compared, and the process data and comparison results are unloaded into a txt document for storage. The reusability of the platform is achieved, the verification time and effort are saved, the problem about the coverage rate is solved, an IP working environment is simulated, and problems existing in an IP are better found.

Description

Technical field [0001] The invention relates to a serial port universal verification platform and method based on SV (SystemVerilog, hardware verification language) language, and belongs to the technical field of chip design. Background technique [0002] With the continuous development of process technology and application fields, the complexity of chips is getting higher and higher, and there are more and more types of interfaces. Correspondingly, the verification task of individual interface IP (Intellectual property, intellectual property) is becoming more and more onerous. The reusability of the interface verification platform is becoming more and more important. Reusing the verification platform can significantly improve the verification efficiency and save labor. [0003] At present, the verification method of the traditional interface verification platform is to use the verilog language. The verifier generates the stimulus signal to test the DUT (Design For Test) chip. The ...

AI Technical Summary

Problems solved by technology

[0006] 1) Every time a traditional simulation verification platform simulates a test case, the environment needs to be rearranged to simulate the next test case;

[0007] 2) The traditional simulation verification platform does not have portability when performing simulation verification of similar IP, and needs to re-arrange the environment, set stimulus signals and test cases;

[0008] 3) The traditional verification platform is more inclined to verify whether the IP can work normally, but it is difficult to simulate the real working environment of the IP. The real IP operates under the action of the driver, and the traditional verification method is difficult to simulate the continuous integrity of the driver to the IP. action, requires a lot of time to construct the environment

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