Clock synchronization circuit of microwave communication system

Abstract

The invention discloses a clock synchronization circuit of a microwave communication system, which comprises a clock synchronization module and an FPGA controller. The FPGA controller is arranged inside the clock synchronization module, and the output end of the FPGA controller is controlled by a control line and a clock. The modules are connected, the input end of the FPGA controller is connected with the system clock through the clock line, the output end of the FPGA controller is also respectively connected with a power supply module and a serial port module, and the output end of the FPGA controller is connected through the RJ45 interface Connect with Ethernet controller, the output end of described Ethernet controller is connected with switchboard through wireless network, the interactive port of described Ethernet controller is connected with system control PC end, utilizes FPGA controller to design clock synchronization circuit , and control the clock jitter elimination circuit based on the phase-locked loop, which can effectively reduce the clock jitter, meet the clock synchronization requirements of the network clock system, and make data transmission more stable.

Description

Technical field [0001] The invention relates to the technical field of clock synchronization circuits, in particular to a clock synchronization circuit of a microwave communication system. Background technique [0002] With the development of network technology, the application of distributed measurement and control systems has become more and more extensive. At the same time, the application of network clock synchronization technology has become more and more extensive, and higher requirements have been put forward for the accuracy of network clock synchronization: [0003] (1) With the continuous increase in system application requirements and the rapid development of integrated circuit technology, large-scale digital circuits often contain multiple clock domains. The design inevitably completes the transfer of digital signals between different clock domains. At this time, How to maintain the stability of the system and successfully complete the transmission of the control signal...

AI Technical Summary

Problems solved by technology

If each level of acquisition node uses an independent on-board clock, as time goes by, the clock frequency error between different acquisition nodes will gradually accumulate, resulting in a gradual increase in the acquisition time deviation. After long-distance transmission, the accumulated jitter of the clock will increase significantly, and the serializer circuit will not work properly when reaching an upper limit

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