A fan-out packaging method

Abstract

The invention discloses a fan-out packaging method, which includes: providing an interposer and a packaging substrate, the interposer includes a base and a wiring area on one side of the base, wherein the base is formed with a hole, and the hole Including a conductive layer, the wiring area is electrically connected to one end of the conductive layer in the hole; the packaging substrate includes a silicon wafer base layer, a pad and a first rewiring layer, and the pad is arranged on the On one side of the base layer of the silicon wafer, the first rewiring layer is arranged on the other side of the base layer of the silicon wafer, wherein the pad is electrically connected to the first rewiring layer; the chip is connected to the intermediary The wiring area of ​​the board is electrically connected to electrically connect the package substrate to the other end of the conductive layer, so that the chip is electrically connected to the pad of the package substrate. Through the above method, the embodiment provided by the present invention can improve the precision of the fan-shaped packaging and prevent the chips from shifting.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a fan-out packaging method. Background technique [0002] With the development of semiconductor technology, the size of the chip is getting smaller and smaller, and the density of I / O (input / output) pins on the surface of the chip is getting higher and higher. High density I / O pins fan out to low density package pins. [0003] At present, the existing fan-out packaging method includes the following process: providing a carrier board, attaching a layer of double-sided adhesive film on the carrier board, attaching the front side of the chip to the adhesive film, plastic sealing the chip, and peeling off the adhesive film. Film and carrier board, forming rewiring layer, ball planting, and dicing on the front side of the chip. [0004] The inventors of the present invention have found in the long-term research process that the above-mentioned fan-out packaging metho...

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Problems solved by technology

[0004] The inventors of the present invention have found in the long-term research process that the above-mentioned fan-out packaging method directly connects the chip to the packaging substrate, and the node spacing of the packaging substrate is relatively large, which cannot be used for high-precision chips; secondly, in the fan-out packaging method, due to When the plastic film is used, the temperature changes during the plastic sealing of the chip will cause the film to shrink and warp due to the difference in the coefficient of thermal expansion (CTE) of the plastic sealing material, chip and carrier board during plastic sealing, which will cause the chip to shift during plastic sealing. The offset causes difficulties in subsequent processes such as lithography alignment

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