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Cache consistency state preset method and system

A high-speed cache and consistency technology, applied in memory systems, instruments, computing, etc., can solve problems such as consumption and long simulation time, and achieve the effect of reducing the time for consistent state jumps

Active Publication Date: 2021-01-19
北京国睿中数科技股份有限公司 +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As a result, it takes a long simulation time to reach a certain cache state

Method used

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  • Cache consistency state preset method and system
  • Cache consistency state preset method and system
  • Cache consistency state preset method and system

Examples

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Embodiment Construction

[0036] Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

[0037] The method and system for presetting the consistent state of the cache according to the embodiments of the present invention will be described below with reference to the accompanying drawings.

[0038] figure 1 It is a flow chart of a method for presetting a consistent state of a cache according to an embodiment of the present invention.

[0039] like figure 1 As shown, according to the method for presetting the coherent state of the cache according to an embodiment of the present invention, in the multiprocessor cache, the coh...

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Abstract

The invention discloses a cache consistency state preset method and system. The method includes: acquiring a random physical address which is mapped to cache, wherein the physical address includes a cache mark bit and a cache index bit; acquiring a consistency state of the random physical address mapped to the catch, wherein a consistency state bit of the physical address includes multiple states,and only one state is allowed for the consistency state bit of the corresponding physical address; writing the physical address and the consistency state in the cache. Therefore, the number of sent instructions and time for state transition are reduced.

Description

technical field [0001] The invention relates to the technical field of high-speed cache, in particular to a method and system for presetting the consistent state of high-speed cache. Background technique [0002] Since the increasing capacity of a single chip allows designers to design multiple processors onto a single chip, this approach is called single-chip multiprocessor. In such a design, multiple processors need to share some resources and some private resources. For the part of the shared cache, the multi-core processor cache coherence protocol is introduced. The key to the cache coherency protocol is to track the state of all shared data blocks. [0003] In a multiprocessor system, that is, in a system in which multiple buffers are allowed to share data, data for the same main memory unit may be duplicated in multiple caches. Cache consistency is mainly to more effectively maintain the consistency of multiple data backups of the same main memory unit. That is, ho...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/0893
CPCG06F12/0893
Inventor 贺庆礼邱剑商家玮
Owner 北京国睿中数科技股份有限公司
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