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Wafer thinning method and thinned wafer structure

A wafer and graphic structure technology, applied in the field of microelectronics, can solve the problems that TAIKO technology is difficult to apply to wafers, and achieve the effect of reducing wafer damage and improving wafer strength

Active Publication Date: 2018-02-13
ZING SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In view of the prior art described above, the purpose of the present invention is to provide a wafer thinning method and a thinned wafer structure to solve the problem that the TAIKO process is difficult to apply to wafers with a diameter of 450mm or more in the prior art

Method used

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  • Wafer thinning method and thinned wafer structure
  • Wafer thinning method and thinned wafer structure
  • Wafer thinning method and thinned wafer structure

Examples

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Embodiment 1

[0054] see image 3 In this embodiment, the wafer is thinned by a patterning process and a wet etching method and a protruding pattern structure is formed on the back of the wafer, including the following steps:

[0055] S101 provides a wafer, the wafer includes a front side and a back side, the front side is formed with IC dies. The wafer is the wafer that needs to be thinned. Usually a silicon wafer. The size of the wafer can be more than 450 mm, and this embodiment takes a wafer with a diameter of 450 mm as an example.

[0056]S102 forming a mask layer on the back surface of the wafer. The mask layer may be a silicon oxide layer or other material layers suitable as a mask. The mask layer can be a single-layer material or a multi-layer composite material. In this embodiment, preferably, the method of forming the mask layer is chemical vapor deposition of TEOS (tetraethylorthosilicate) material.

[0057] S103 Photolithographically form a patterned photoresist layer on t...

Embodiment 2

[0062] In this embodiment, on the basis of the technical solution of the first embodiment, the wafer is thinned by combining the grinding process and the wet etching method. The difference from Embodiment 1 is that before the mask layer is formed on the back of the wafer, the wafer is first thinned to a certain thickness by grinding or wet etching on the back of the wafer, and then used In the method of Embodiment 1, a protruding pattern structure is formed on the back of the wafer, and the wafer is thinned to the final required thickness.

[0063] Alternatively, after the protruding pattern structure is obtained on the back of the wafer, the wafer is thinned to the final required thickness by grinding on the back of the wafer. Specifically, a grinding head with a smaller diameter may be used to grind the part other than the protruding pattern structure on the back of the wafer.

Embodiment 3

[0065] In this embodiment, the wafer is thinned by a grinding process and a protruding pattern structure is formed on the back of the wafer. The specific method is: grinding on the back of the wafer, and only retaining the ring located at the outer edge of the wafer. area and the part outside the area of ​​the intersection graph located within the circular area.

[0066] In this embodiment, preferably, two grinding heads with different diameters can be used for grinding, and the grinding path of the grinding head can be planned according to the required graphic structure. Larger grinding heads are used for grinding larger areas.

[0067] In addition, on the basis of grinding to form the desired pattern structure, wet etching can also be combined to obtain a thinned wafer with a better surface state.

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Abstract

The invention provides a wafer thinning method and a thinned wafer structure. The method includes the following steps thata wafer is provided,wherein the wafer includes a front surface and a back surface,and an IC bare core is formed on the front surface; and the wafer is thinned and a protruding pattern structure is formed on the back surface of the wafer, wherein the pattern structure includes an annular structure located on a peripheral edge of the wafer and a cross-pattern structure located in the annular structure. The wafer thinning method and the thinned wafer structure utilize a thinning process to form a protruding cross-pattern structure and an annular edge on the back surface of the wafer, thereby improving the strength of the wafer and reducing wafer breakage. By using the technical scheme of the wafer thinning method and the thinned wafer structure, larger size thinning and application of the wafer can be achieved.

Description

technical field [0001] The invention relates to the technical field of microelectronics, in particular to a wafer thinning method and a thinned wafer structure. Background technique [0002] As applications such as memory and power devices move toward smaller size and higher performance, there is a growing need for thinner wafers. Thinner wafers can bring many benefits, including ultra-thin packaging and the resulting smaller form factor, including improved electrical performance and better thermal performance. At this stage, the most common thinning process for semiconductor applications is grinding. The TAIKO process is a wafer back grinding technology developed by Disco Technology Co., Ltd. This technology is different from the previous back grinding. When grinding the wafer, the peripheral edge of the wafer will be kept, and only the inner circle will be processed. Grinding for thinning. This kind of TAIKO wafer with margins on the periphery of the wafer has important...

Claims

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Application Information

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IPC IPC(8): H01L21/02H01L21/304H01L21/306H01L21/308H01L21/3105H01L21/311
CPCH01L21/02H01L21/304H01L21/30608H01L21/308H01L21/3105H01L21/311H01L21/31111
Inventor 三重野文健
Owner ZING SEMICON CORP