Multi-Threaded Translation And Transaction Re-Ordering For Memory Management Units

Abstract

Systems and methods relate to performing address translations in a multithreaded memory management unit (MMU). Two or more address translation requests can be received by the multithreaded MMU and processed in parallel to retrieve address translations to addresses of a system memory. If the address translations are present in a translation cache of the multithreaded MMU, the address translations can be received from the translation cache and scheduled for access of the system memory using the translated addresses. If there is a miss in the translation cache, two or more address translation requests can be scheduled in two or more translation table walks in parallel.

Description

[0001] Priority claim under 35 U.S.C. § 119 [0002] This patent application claims Ser. No. 62 / 168,712, filed May 29, 2015, entitled "MULTI-THREADED TRANSLATION AND TRANSACTION RE-ORDERING FORMEMORY MANAGEMENT UNITS" priority to the provisional application, which is assigned to the present assignee and is hereby expressly incorporated by reference. technical field [0003] The disclosed aspects relate to a memory management unit (MMU), and more particularly, the illustrative aspects relate to a multi-threaded MMU configured to handle multiple translations in parallel. Background technique [0004] A memory management unit (MMU) is configured to perform address translation (and other memory management functions) for a processor or peripheral device (often referred to as an upstream client or device). For example, the MMU may include a translation lookaside buffer (TLB) as known in the art to perform virtual to physical memory address translation. [0005] see figure 1 ,...

AI Technical Summary

Problems solved by technology

During the time to get the transition for the client input transaction 116 at the top of the transaction queue 110, the MMU 104 stalls, and thus the performance of the MMU 104 degrades

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