A method for increasing the thickness difference between the storage unit area and the control circuit area of ​​the side wall

Abstract

The invention provides a method for improving the thickness difference between the storage unit area and the control circuit area, which is suitable for non-volatile flash memory. Depositing the first SiO2 layer and the layer, and depositing the second SiO2 layer on the substrate by using the second reaction pressure, the first SiO2 layer, the layer and the second SiO2 layer constitute the first sidewall covering the sidewall of the gate structure and the covering spacer structure For the second sidewall of the sidewall, the first reaction pressure is greater than the second reaction pressure, and the thickness of the second SiO2 layer in the first sidewall is smaller than the thickness of the second SiO2 layer in the second sidewall. Beneficial effects of the present invention: it is possible to increase the thickness difference between the non-volatile flash storage unit area and the control circuit area, improve the high-temperature breakdown voltage of the control circuit area, and increase the ion implantation rate under the premise of ensuring the performance of the storage unit area. Adjust the space and improve the performance of the MOS tube.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for improving the thickness difference between the sidewalls of the memory cell region and the control circuit region. Background technique [0002] The thickness of the sidewall directly affects the ion implantation of the source and drain S / D of the MOS tube, which in turn determines the electrical performance of the MOS tube. At the same time, the performance of the memory cell region (CELL region) and the control circuit region (PERI region) depends on the win-win performance. The thickness difference between the two side walls. In the existing process, the sidewalls of the CELL region and the PERI region are simultaneously completed with an oxide-nitride-oxide (ONO) structure, and the thickness difference between the two is about 4 nm. [0003] The thickness difference between the side walls of the CELL area and the PERI area determines whether ...

AI Technical Summary

Problems solved by technology

Under the current manufacturing process of flash memory, the PERI area meets expectations, and the CELL area is almost filled with sidewalls; on the contrary, the thickness of the sidewalls in the PERI area is too thin, resulting in the S / D of the source and drain of the MOS transistor and the lightly doped drain ( The distance of Low doped drain (LDD) is shortened, and the high temperature breakdown voltage (Breakdown Voltage, BV) of MOS tube is too small, etc.

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