Method for improving sidewall thickness difference of storage unit area and control circuit area

Abstract

The invention provides a method for improving the sidewall thickness difference of a storage unit area and a control circuit area, which is applicable to a nonvolatile flash memory. The method comprises the steps of providing a composite structure; sequentially depositing a first SiO2 layer and a Si3O4 layer on a substrate by adopting first reaction pressure in a reaction chamber, depositing a second SiO2 layer on the substrate by adopting second reaction pressure, wherein the first SiO2 layer, the Si3O4 layer and the second SiO2 layer form a first side wall covering the side wall of a gate structure and a second side wall covering the side wall of a spacing structure, the first reaction pressure is greater than the second reaction pressure, and the thickness of the second SiO2 layer in the first side wall is less than the thickness of the second SiO2 layer in the second side wall. The method has the beneficial effects that the side wall thickness difference of the storage unit area and the control circuit area of the nonvolatile flash memory can be improved, the high-temperature breakdown voltage of the control circuit area is improved under the premise of ensuring the performanceof the storage unit area, the adjustment space of ion implantation is increased, and the performance of an MOS transistor is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for increasing the thickness difference between a storage unit area and a control circuit area. Background technique [0002] The thickness of the sidewall directly affects the ion implantation of the source and drain S / D of the MOS tube, which in turn determines the electrical performance of the MOS tube. At the same time, the win-win performance of the memory cell area (CELL area) and the control circuit area (PERI area) depends on The thickness difference between the two side walls. In the existing manufacturing process, the side walls of the CELL region and the PERI region are simultaneously completed with an oxide-nitride-oxide (ONO) structure, and the thickness difference between the two is about 4nm. [0003] The thickness difference between the side walls of the CELL region and the PERI region determines whether the electrical performance of ...

AI Technical Summary

Problems solved by technology

Under the current manufacturing process of flash memory, the PERI area meets expectations, and the CELL area is almost filled with sidewalls; on the contrary, the thickness of the sidewalls in the PERI area is too thin, resulting in the S / D of the source and drain of the MOS transistor and the lightly doped drain ( The distance of Low doped drain (LDD) is shortened, and the high temperature breakdown voltage (Breakdown Voltage, BV) of MOS tube is too small, etc.

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