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Polynomial-based GF(2^n) multiplier

A technology based on polynomials and polynomials, which is applied to calculations using residual algorithms, calculations using non-numerical representations, etc., can solve the problems of multiplier size reduction and occupy a lot of space, so as to reduce complexity and space complexity The effect of reducing the overall volume

Inactive Publication Date: 2018-03-06
TSINGHUA UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] However, to perform the above-mentioned modulo calculation, more XOR gates and AND gates need to be installed in the calculation circuit of the multiplier, which takes up more space and is not conducive to the reduction of the size of the multiplier.

Method used

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Embodiment Construction

[0034] In order to make the object, technical solution and advantages of the present invention clearer, the specific implementation of the polynomial base GF(2^n) multiplier of the present invention will be described below in conjunction with the accompanying drawings. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0035] The polynomial base GF (2^n) multiplier of the present invention is used to utilize the circuit to calculate the element in the polynomial ring R[x] and product of . Among them, a i ,b i ∈R, R is a ring.

[0036] The multiplier of an embodiment of the present invention, such as figure 1 It includes a quotient seeking module 100 , an intermediate modular multiplication calculation module 200 and a summation module 300 .

[0037] Wherein, the quotient module 100 is used to calculate two polynomials for modular multiplication and The product AB...

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Abstract

The invention discloses a polynomial-based GF(2^n) multiplier. The multiplier is used for calculating a product of an element A and an element B (shown in the description) in a polynomial ring R[x]. The multiplier comprises a quotient solving module, an intermediate modular multiplication calculation module and a summation module, wherein the quotient solving module is used for calculating a quotient q obtained after the product AB of the polynomial A and the polynomial B (shown in the description) for modular multiplication is divided by an n-degree polynomial (f(x)-1); the intermediate modular multiplication calculation module is used for calculating modular multiplication between the product AB of the polynomial A and the polynomial B and the polynomial (f(x)-1) to obtain an intermediate modular value (c+q); and the input end of the summation module is connected with the output end of the intermediate modular multiplication calculation module and the output end of the quotient solving module, and the summation module is used for subtracting the quotient q from the intermediate modular value (c+q) to obtain a modular multiplication value c of the product AB of the polynomial A and the polynomial B relative to a polynomial f(x). Through the multiplier, a direct module solving step relative to the polynomial f(x) is unavailable, less XOR gates and AND gates are available on average, and therefore the space complexity of the multiplier is lowered under the condition that time complexity is not improved. The complexity of a multiplier integrated circuit is lowered, and the overall volume of the multiplier is shrunk beneficially.

Description

technical field [0001] The invention relates to the technical field of digital signal processing, in particular to a polynomial base GF(2^n) multiplier. Background technique [0002] f(x)=x n +x k +1(n>2) is an irreducible polynomial of degree n on GF(2), then the finite field GF(2 n ) := GF(2)[x] / (f(u)) All elements under the polynomial basis {x i |0≤i≤n-1} to represent. For two elements in a given domain and Then calculate the product of A and B The conventional method is accomplished in the following two steps. [0003] (1) Traditional polynomial multiplication: Each item is specifically: [0004] [0005] (2) Modulo operation [0006] [0007] However, to perform the above-mentioned modular operation, more XOR gates and AND gates need to be arranged in the calculation circuit of the multiplier, which takes up a lot of space and is not conducive to the reduction of the size of the multiplier. Contents of the invention [0008] Based on this, it i...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/72
Inventor 樊海宁张嘉俊
Owner TSINGHUA UNIV
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