Page table cache access method, page table cache, processor chip and storage unit

Abstract

The invention discloses a page table cache access method, a page table cache, a processor chip and a storage unit. The method comprises the steps that a first request sent by a processor is received;a first big virtual page number corresponding to a first virtual address and a first position of a first virtual page, corresponding to the first virtual address, in a first big virtual page are determined; whether a first table item corresponding to the first big virtual page number exists in a table item set is determined; according to a value of a bit, corresponding to the first position, in avalid instruction field in the first table item, whether the first virtual page is mapped by the first table item is determined; according a value of an element, corresponding to the first position, in an index field in the first table item, a second position of a first physical page, corresponding to the first virtual page, in a first big physical page identified with a first big physical frame number is determined; according to the first big physical frame number and the second position, a first physical frame number is determined; and the first physical frame number is sent to the processor. Through the embodiment, valid capacity of the page table cache can be increased.

Description

technical field [0001] The present invention relates to the field of information technology, and more specifically, relates to a method for accessing a page table cache, a page table cache, a processor chip and a storage unit. Background technique [0002] When a central processing unit (Central Processing Unit, CPU) executes a program, the addresses in the program are all virtual addresses. When the operating system loads a program into memory, it allocates available physical memory address space for the program. At this time, the operating system will map the virtual address of the program to a specific physical address according to the actual physical address. This kind of mapping takes page (Page) as a unit, and a page is usually 4KB. When the operating system performs memory management, it divides the physical address space into consecutive pages. Likewise, the program's own virtual address space is divided into contiguous pages. Mapping is to map a virtual page to ...

AI Technical Summary

Problems solved by technology

The capacity of the TLB is very limited, much smaller than the size of the page table, so TLB Miss often occurs, and TLB Miss will increase the running time of the program

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