Decoupled processor instruction window and operand buffer

Abstract

A processor core in an instruction block-based microarchitecture is configured such that the instruction window and operand buffer are decoupled to operate independently, wherein the instructions in the block are not associated with resources such as being maintained in the operand buffer The control bits and operands in ) are strictly bound. Instead, pointers are established between the instructions in the blocks and resources so that control states can be established for flushed instruction blocks (ie, instruction blocks that are reused without being re-fetched from the instruction cache) by following these pointers. This decoupling of the instruction window from the operand space can provide greater processor efficiency, especially in multicore arrays that utilize flushing (for example, when executing program code that uses tight loops), because operand and control bits are pre-validated.

Description

Background technique [0001] Designers of instruction set architectures (ISAs) and processors make tradeoffs between power consumption and performance. For example, if the designer selects an ISA with instructions that deliver higher performance, the processor's power consumption may also be higher. Alternatively, performance may be lower if the designer chooses an ISA with instructions that consume less power. Power consumption may be related to the amount of a processor's hardware resources, such as an arithmetic logic unit (ALU), cache lines, or registers, used by an instruction during execution. Using a large number of such hardware resources can deliver higher performance at the expense of higher power consumption. Alternatively, using fewer such hardware resources can result in lower power consumption at the expense of lower performance. A compiler can be used to compile high-level code into instructions compatible with the ISA and processor architecture. Contents of...

AI Technical Summary

Problems solved by technology

For example, if the designer selects an ISA with instructions that deliver higher performance, the processor may also consume more power

Alternatively, performance may be lower if the designer chooses an ISA with instructions that consume less power

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