Batch allocation of instruction blocks to processor instruction windows

Abstract

A processor core in an instruction block-based microarchitecture includes a control unit that distributes instructions into instruction windows in a batch fashion by simultaneously fetching instruction blocks and associated resources including control bits and operands. Such batch allocation supports increased efficiency of processor core operations by enforcing consistent management and policy enforcement across all instructions in a block during execution. For example, when a block of instructions branches back on itself, it can be reused during a flush rather than being refetched from the instruction cache. Since all resources for that instruction block are in one place, instructions can stay in place and only the valid bit needs to be cleared. Bulk allocation also supports operand sharing by instructions in a block and explicit message passing between instructions.

Description

Background technique [0001] Designers of instruction set architectures (ISAs) and processors make tradeoffs between power consumption and performance. For example, if the designer selects an ISA with instructions that deliver higher performance, the processor's power consumption may also be higher. Alternatively, performance may be lower if the designer chooses an ISA with instructions that consume less power. Power consumption may be related to the amount of a processor's hardware resources, such as an arithmetic logic unit (ALU), cache lines, or registers, used by an instruction during execution. Using a large number of such hardware resources can deliver higher performance at the expense of higher power consumption. Alternatively, using fewer such hardware resources can result in lower power consumption at the expense of lower performance. A compiler can be used to compile high-level code into instructions compatible with the ISA and processor architecture. Contents of...

AI Technical Summary

Problems solved by technology

For example, if the designer selects an ISA with instructions that deliver higher performance, the processor may also consume more power

Alternatively, performance may be lower if the designer chooses an ISA with instructions that consume less power

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