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Packing method and equipment of fpga

A device that meets the preset technology, applied in the field of FPGA, can solve problems such as poor packing results, and achieve the effect of good packing results and reduced quantity

Active Publication Date: 2021-05-28
SHANGHAI FUDAN MICROELECTRONICS GROUP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, when using the existing boxing method to box each logic unit in the netlist file, the final PB usually only satisfies one or some of the constraints in all the constraints, and the boxing result is poor.

Method used

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  • Packing method and equipment of fpga
  • Packing method and equipment of fpga
  • Packing method and equipment of fpga

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Embodiment Construction

[0026] At present, to box each logic unit in the netlist file, a boxing algorithm aiming at one or several constraint conditions is usually used to perform the boxing operation. Specifically, using the binning algorithm, a logical unit is first selected as a seed to generate a physical unit, and then the attractive factors of other logical units are calculated according to the constraints targeted by the algorithm, and the logical unit with the largest attractive factor is absorbed into all in the generated physical unit. Then repeat the above process until the physical unit cannot absorb other logical units. Then select the next seed to generate a new physical unit, and fill the new physical unit according to the above steps until all logical units are loaded into different physical units.

[0027] Due to the increasing scale of circuit design, the user's timing constraints are becoming more and more complex, and the structure of the physical unit of the FPGA is also becomin...

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Abstract

An FPGA packing method and device. The method includes: when receiving the netlist file, modifying the netlist file according to the design rule of the physical unit; according to the first packing rule, packing each logic unit in the modified netlist file boxes to obtain multiple physical units; repeat the following operations until a group that satisfies the preset conditions is obtained as the final physical unit: analyze whether the circuit composed of all the current groups meets all the preset constraints, and combine all the current groups Constraints that are not satisfied by the composed circuits are merged for the current group, where the constraints include more than two. By applying the above method, the packing process of FPGA can be optimized and better packing results can be obtained.

Description

technical field [0001] The invention relates to the field of FPGA technology, in particular to a packing method and equipment for FPGA. Background technique [0002] Field Programmable Gate Array (Field-Programmable Gate Array, FPGA) is further developed on the basis of programmable devices such as Programmable Logic Array (Programmable Logic Array, PAL) and General Logic Array (Generic Logic Array, GAL). of. As a semi-custom circuit in the field of application-specific integrated circuits (ASIC), FPGA not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of original programmable device gate circuits. [0003] In the FPGA design process, it usually includes steps such as logic synthesis, packing and physical design in sequence. Among them, the so-called logic synthesis refers to the software text used to describe the functions realized by the FPGA, which is compiled, optimized, converted and synthesized according to ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/34G06F111/04
CPCG06F30/34G06F2111/06
Inventor 吴昌杨琼华李佐渭徐烈伟
Owner SHANGHAI FUDAN MICROELECTRONICS GROUP