Memory sharing method and multiprocessor-based terminal device

Abstract

The invention relates to the field of computers and discloses a memory sharing method and a multiprocessor-based terminal device. According to the method, a first processor serving as a data receiverapplies for N cache regions from a system heap space in a starting process of an operation system; the cache regions are ensured to be applied for by the receiver; the first processor stores addressesof the N cache regions in N sections in sequence, so that data communication can be performed through a public shared memory; a second processor serving as a data sender writes data in the cache regions corresponding to L sections in sequence; and the first processor reads the data of the cache regions corresponding to the L sections and then releases the cache regions corresponding to the L sections, so that the receiver obtains the data of the sender through the shared memory, and the cache regions are ensured to be released by the receiver. Multiple processors of the same terminal is managed in a unified way by adopting a memory management mode of applying for and releasing the cache regions by the receiver during the data communication based on the shared memory.

Description

technical field [0001] The invention relates to the computer field, in particular to a memory sharing method and a multiprocessor-based terminal device. Background technique [0002] Multiprocessor chips are widely used in various embedded devices. Data communication between processors is based on shared memory. This shared memory can be accessed by multiple processors to read and write data separately. Operation, at present, in scenarios that require high real-time data interaction, the following memory management methods are basically adopted: the shared memory is divided into two areas, the data area and the free area, and are managed by queues respectively. Among them, In the data area, several buffer areas are arranged together to form a data queue. In the idle area, a number of idle buffer areas without valid data are arranged together to form an idle queue. Moreover, the buffer area is applied by the processor as the sender, and the Released by the receiving processo...

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Problems solved by technology

[0003] However, in the process of realizing the invention, the inventors of the present application found that, in the above-mentioned memory management method, the management of the idle queue and the data queue are separately managed by the sender processor and the receiver processor, which requires more mutual exclusion. Logic can achieve common management, and the difficulty of debugging also increases. Once an error occurs in memory usage, it is necessary to grab the data structures on the two processors at the same time to locate, which requires high debugging methods. In particular, the queue buffer area needs It is pre-allocated and independent of the heap space of the operating system. Moreover, this part of the pre-planned buffer area defined by the size and boundary will change according to different hardware resources. When changing the product form, the plan needs to be adjusted accordingly, and the portability is poor.

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