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Flow pinning in a server on a chip

A server and single-chip technology, applied in the field of streaming pinning, can solve the problems of space occupation, network interface card cost, expensive power and latent time, etc.

Active Publication Date: 2018-05-11
AMPERE COMPUTING LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, network interface cards are expensive in terms of cost, power, and latency, and they also take up a lot of space in the system

Method used

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  • Flow pinning in a server on a chip
  • Flow pinning in a server on a chip
  • Flow pinning in a server on a chip

Examples

Experimental program
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Embodiment Construction

[0018] Embodiments are provided for a system-on-a-chip or server-on-a-chip that performs stream pinning, where packets or streams of packets are placed into specific queues, where each queue is associated with a multiprocessor / multicore system or Corresponding cores in single-chip servers. With each packet stream, or stream, assigned to a specific processor, the single-chip server can process and ingest packets from multiple queues in parallel from multiple streams from the same single Ethernet interface. Each of the queues can issue an interrupt to its assigned processor, allowing each of the processors to simultaneously receive packets from its corresponding queue. Thus, packet processing speed is increased by receiving and processing packets in parallel for different streams.

[0019] Stream pinning in this way associating each queue with a corresponding core allows for increased throughput of incoming traffic with multiple streams. Cache and CPU usage are also improved b...

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Abstract

A system on a chip or a server on a chip that performs flow pinning. Packets or streams of packets are enqueued to specific queues, wherein each queue is associated with a respective core in a multiprocessor / multi-core system or server on a chip. With each stream of packets, or flow, assigned to a particular processor, the server on a chip can process and intake packets from multiple queues from multiple streams from the same single Ethernet interface in parallel. Each of the queues can issue interrupts to their assigned processors, allowing each of the processors to receive packets from theirrespective queues at the same time.

Description

technical field [0001] This disclosure is about flow pinning in a server on a chip. Background technique [0002] In a computing network, an Ethernet interface can receive packets from many different Ethernet connections or streams. In some systems, the stream of these packets is processed serially because it is received by a dedicated processor. In other conventional systems, the traffic of these packets is handled by a peripheral network interface card that places the packets and / or traffic into special queues that are associated with the multi-core processor Associated with a given CPU (Central Processing Unit) in . However, network interface cards are expensive in terms of cost, power, and latency, and also take up a lot of space in the system. [0003] The above description only provides a content-related overview of current technologies for stream pinning in a system on a chip, and is not exhaustive. Contents of the invention [0004] In an exemplary embodiment, ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/883H04L49/9015
CPCH04L47/50H04L47/621H04L49/90
Inventor K·丘德加尔K·桑卡兰
Owner AMPERE COMPUTING LLC