Integrated circuit device with self-test capability and method for self-testing integrated circuit

Abstract

An integrated circuit device with self-test capability includes pattern generator, result storage and testable logic. The testable logic includes a plurality of scan channels, each of which is respectively coupled between the pattern generator and the result store. The self-test controller is arranged to oversee self-tests on the testable logic to generate self-test result data, which is stored in the result store. A processing resource is also coupled to the self-test controller and between the pattern generator and the results store, the processing resource being capable of evaluating self-test result data stored in the results store. The testable logic comprises a processing resource arranged to cooperate with the self-test controller so that the self-test is also with respect to the processing resource and the processing resource is able to evaluate the self-test result data after the self-test.

Description

technical field [0001] The present invention relates to self-test capable integrated circuit devices, for example of the type including testable logic (including processing resources). The invention also relates to a method of self-testing an integrated circuit, such as a method comprising self-testing of testable logic, including processing resources. Background technique [0002] To ensure reliable operation, integrated circuits require testing. Depending on what is required for testing, different testing techniques are available. However, testing integrated circuits is becoming increasingly complex and requires new techniques to meet new safety regulations. For example, there is an increased need for the deployment of so-called "field" test scenarios for integrated circuits. Indeed, in the automotive industry, logic built-in self-test (LBIST) mechanisms are employed to provide on-site testing in compliance with recent standards for functional safety (such as ISO 26262)...

AI Technical Summary

Problems solved by technology

Decision logic is provided in addition to the logic to be scanned, however like the on-chip test processing capability of US2016 / 033571, the decision logic itself is not tested

[0006] Even for implementations where the logic being scanned and the logic controlling the scan scan each other in turn, using dedicated logic for testing the logic to be scanned represents a waste of die space

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