A Simulated Annealing Method for Detailed Layout of FPGA

Abstract

A simulated annealing method for FPGA detailed layout, calculate the initial temperature of simulated annealing according to the initial layout formed after the legalized layout, move the unit module to optimize the current layout, according to the acceptance rate of the unit module movement, based on the initial temperature The temperature value of the target is adjusted iteratively with a fixed ratio, the normalization coefficient is used to normalize the target value of multiple targets, and the temperature proportional coefficient is used to correct and iteratively calculate the temperature value of the single target after iterative adjustment, and the multi-target temperature value is obtained. temperature value. On the basis of single-objective optimization, the present invention performs normalization processing and proportional coefficient adjustment on multi-objective optimization, ensures the consistency of optimization results and the effectiveness of multi-objective optimization, and eliminates the need for cooling strategies in traditional simulated annealing methods. The unreasonable impact on the quality and speed of the layout, the adjusted temperature is more conducive to the improvement of the quality and speed of the layout.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a simulated annealing method for FPGA detailed layout. Background technique [0002] FPGA adopts the concept of logic cell array LCA (Logic Cell Array), which includes three parts: configurable logic module CLB (Configurable Logic Block), input and output module IOB (Input Output Block) and internal wiring (Interconnect). Field Programmable Gate Array (FPGA) is a programmable device. Compared with traditional logic circuits and gate arrays (such as PAL, GAL and CPLD devices), FPGA has a different structure. FPGA uses a small look-up table (16×1RAM) to implement combinatorial logic, each look-up table is connected to the input of a D flip-flop, and the flip-flop drives other logic circuits or drives I / O, thus forming a combinatorial The logic function can also realize the basic logic unit module of the sequential logic function, and these modules are connected to each oth...

AI Technical Summary

Problems solved by technology

[0006] The traditional simulated annealing method is difficult to ensure that the multi-objective optimization function only optimizes a single objective and the single-objective optimization function optimizes the consistency of a single objective. The unreasonable cooling strategy in the traditional simulated annealing method affects the quality and speed of the layout.

Images