Dynamic random memory unit with educed design area and method for manufacturing the same

Abstract

The invention provides a dynamic random memory unit with a reduced design area and a method for manufacturing the same, wherein the dynamic random memory unit and the method are applied to the field of semiconductor memory device manufacturing. Each dynamic random memory unit consists of a transistor and a capacitor; a gate electrode of the transistor is used for realize conduction of a transmission channel between a bit line and the capacitor under control of a word line voltage. Each dynamic random memory unit is prepared as follows: forming a horizontally expanded panel on a semiconductor substrate; forming gate electrodes of the transistor at two sides of the panel; forming a bit line connection port connected with the bit line electrically at a predetermined position above the panel;and forming the capacitor at one side of the gate electrode. The capacitor and the transmission channel generate electric connection. The dynamic random memory unit has the following beneficial effect: the design area of the dynamic random memory unit is reduced by means of sharing the panel and the bit line connection port.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a DRAM unit with reduced design area and a manufacturing method thereof. Background technique [0002] Generally, a DRAM is composed of a plurality of DRAM units. At this time, each of the plurality of DRAM cells is composed of a transistor (CTR) and a capacitor. The capacitor can store charges, and the transistor (CTR) forms a transmission channel (TCH) that connects the bit line and the capacitor according to the voltage applied to the gate electrode. [0003] At the same time, with the high integration of DRAM, research on a DRAM cell (DRAM Cell) with reduced design area is being carried out. Especially in the case of ensuring a certain level of cell transistor transfer channel length, techniques for reducing the design area are being actively pursued. [0004] Vertical type filling with cell transistors is one of these techniques for reducing the design area of ​...

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Problems solved by technology

[0005] However, there is a bottleneck in reducing the design area of ​​the DRAM because each DRAM in such a cell transistor with a vertical type fill needs a fill

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