SRAM read and write indirect testing device and method based on LabVIEW

A test device and indirect technology, applied in static memory, instruments, etc., can solve the problems of inflexible control configuration of direct reading and writing SRAM, unfriendly test interface, etc., and achieve simple test interface, simple and convenient timing adjustment, and intuitive interface Effect

Pending Publication Date: 2018-07-06
YULIN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] What the present invention will solve is that the test interface of the above-mentioned direct read-write SRAM is unfriendly; The technical problem that the control configuration of direct read-write SRAM is inflexible, provides the SRAM read-write indirect test device and method based on LabVIEW

Method used

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  • SRAM read and write indirect testing device and method based on LabVIEW
  • SRAM read and write indirect testing device and method based on LabVIEW
  • SRAM read and write indirect testing device and method based on LabVIEW

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Embodiment Construction

[0021] Below in conjunction with accompanying drawing, the present invention is described in further detail:

[0022] like figure 1 Shown is the IS61LV10248 chip write operation timing diagram, in which:

[0023] t WC Indicates Write Cycle Time;

[0024] t SCE Indicates CE to Write End;

[0025] t AW Indicates Address Setup Time to Write End;

[0026] t HA Indicates Address Hold from Write End;

[0027] t SA Indicates Address Setup Time;

[0028] t PWE1 Indicates WE Pulse Width;

[0029] t PWE2 Indicates WE Pulse Width (OE=LOW);

[0030] t SD Indicates Data Setup to Write End;

[0031] t HD Indicates Data Hold from Write End;

[0032] t HZWE Indicates WE LOW to High-Z Output;

[0033] t LZWE Indicates WE HIGH to Low-Z Output.

[0034] Depend on figure 1 It can be known that the IS61LV10248 chip is valid for writing data, it must satisfy the chip select signal CE / , and the write enable WE / is low; at the same time, it must satisfy the address signal ADRESS...

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Abstract

The invention discloses an SRAM read and write indirect testing device and an SRAM read and write indirect testing method based on LabVIEW, which are used for solving the technical problems that a testing interface for the existing direct reading and writing SRAM is not friendly and the control configuration for the direct reading and writing SRAM is not flexible. An FPGA circuit module is used for receiving SRAM signal parameter data sent from a serial port; a tested chip IS61LV10248 circuit module is used as a tested object; an SRAM read and write indirect testing control panel module basedon the LabVIEW is used for compiling a front panel human-computer interface; a write operation control command module is used for executing SRAM write operation; a data reading command module is usedfor executing SRAM read operation; an underlying serial port driving module is used for performing data interaction. The invention has the beneficial effects as follows: the testing interface is simple and intuitive, and a user interface can be created very conveniently; timing parameters are convenient to adjust; the integration is high, the reliability is good, and the external interference is less.

Description

technical field [0001] The invention belongs to the field of integrated circuit and chip testing, and in particular relates to an SRAM read-write indirect testing device and method based on LabVIEW. Background technique [0002] With the development of society, random memory chips are used more and more widely and can be seen everywhere. Although there are various types and quantities of SRAM chips, it is difficult for us to judge the source of these SRAM chips and the quality of the chips. There are several reasons for this: First, some are imitation SRAM chips; second, some are SRAM chips removed from the device. It is difficult to judge the source of the SRAM chip and the quality of the chip by relying on the naked eye. It is necessary to identify these SRAM chips: first, not to waste resources; second, to ensure the user's design performance requirements; third, to protect the manufacturer's original design. This requires us to invent a test method for SRAM chips, whi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/56
CPCG11C29/56G11C29/56012G11C29/56016G11C2029/5602
Inventor 党学立王雯
Owner YULIN UNIV
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