Method for quickly implementing optimal binary tree based on hardware FPGA
An optimal binary tree and binary tree technology, applied in the direction of software design, etc., can solve problems such as slow speed, complexity, and deep dependence of binary tree nodes, and achieve the effect of improving the generation speed and being easy to implement
Active Publication Date: 2018-07-24
武汉中元华电电力设备有限公司
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[0002] The early binary tree was mainly implemented by software, which was too slow, while the hardware implementation only used a single-level cache to seriously affect the generation speed of the binary tree. At the same time, the statistics of the depth of the binary tree nodes depended too much on the generation of branch nodes and leaf nodes. This makes the algorithm clumsy and complicated
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[0022] The present invention will be further described in conjunction with the accompanying drawings.
[0023] Such as figure 1 Shown in, a kind of method of the present invention realizes optimal binary tree fast based on hardware FPGA, this method comprises binary tree construction module, node association information statistics module, depth generation module, binary tree generation module, all above-mentioned modules are all adopted hardware FPGA realization, It is characterized in that it is carried out in the following steps: Step 1, the binary tree construction module carries out the construction of binary tree to the data that has been statistically sorted, and divides into two levels of FIFO (First Input First Output) to cache, the first level stores leaf nodes, and the second level The first two data are taken out from the two-level FIFO each time, and the smallest two data among the four data are constructed as a branch node and stored in the second-level FIFO, and ...
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The invention relates to a method for quickly implementing an optimal binary tree based on hardware FPGA. The method comprises a binary tree construction module, a node association information statistics module, a depth generation module and a binary tree generation module, the method is characterized by comprising the following steps that the binary tree construction module continuously extractsdata from caches to construct branch nodes and leaf nodes, the node association information statistics module counts the relationship between each branch node and the leaf nodes, after the statisticsis completed, the depth generation module generates depth information of the leaf nodes based on the relationship between the branch nodes and the leaf nodes provided by the node association information statistics module, and finally the binary tree generation module can recover the optimal binary tree according to the depth information of the leaf nodes. The method is simple and efficient, and achieves the purpose of rapidly generating the optimal binary tree.
Description
technical field [0001] The invention relates to a method for quickly realizing an optimal binary tree based on a hardware FPGA, and the method can be applied to all fields of generating an optimal binary tree for data that has been statistically sorted. Background technique [0002] The early binary tree was mainly implemented by software, which was too slow, while the hardware implementation only used a single-level cache to seriously affect the generation speed of the binary tree. At the same time, the statistics of the depth of the binary tree nodes depended too much on the generation of branch nodes and leaf nodes. This makes the algorithm clumsy and complicated. Contents of the invention [0003] In order to overcome the problems in the above-mentioned prior art, the present invention provides a method for quickly realizing an optimal binary tree based on a hardware FPGA, and divides the original binary tree method into a binary tree construction module, a node associ...
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CPCG06F8/22
Inventor 危必波陈伯芳袁成伟郑蓉詹万鹏王晓斌
Owner 武汉中元华电电力设备有限公司