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Interconnection structure and manufacturing method thereof

A manufacturing method and interconnection technology, which are used in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., to prevent circuit bridging defects and increase overlap margins

Active Publication Date: 2021-03-05
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this way, two adjacent upper-layer conductive components will generate a bridging path (bridging path) through the exposed lower-layer conductive component, thereby causing a circuit bridging (circuit bridging) defect.

Method used

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  • Interconnection structure and manufacturing method thereof
  • Interconnection structure and manufacturing method thereof
  • Interconnection structure and manufacturing method thereof

Examples

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Embodiment Construction

[0027] Figure 1A to Figure 1D It is a cross-sectional view of the manufacturing process of the interconnection structure according to an embodiment of the present invention.

[0028] First, please refer to Figure 1A , forming a dielectric layer 102 on the substrate 100 , wherein the dielectric layer 102 has an opening 104 . The substrate 100 can be a single-layer substrate or a multi-layer substrate, and other film layers (not shown) or semiconductor devices (not shown) can be formed thereon. The material of the dielectric layer 102 is, for example, silicon oxide. The method for forming the dielectric layer 102 is, for example, chemical vapor deposition. The opening 104 is, for example, a contact hole, a via hole or a trench. A method for forming the opening 104 is, for example, performing a patterning process on the dielectric layer 102 .

[0029] Next, please refer to Figure 1B , the barrier layer 106 can be optionally formed on the surface of the opening 104 . The ...

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PUM

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Abstract

An interconnection structure includes a substrate, a dielectric layer, a first conductive pattern and a second conductive pattern. The dielectric layer is disposed on the base and has an opening. The first conductive pattern is disposed in the opening. The second conductive pattern is disposed on the first conductive pattern and exposes an exposed portion of the first conductive pattern. The exposed portion of the first conductive pattern has a gap.

Description

technical field [0001] The present invention relates to a conductive structure and its manufacturing method, and in particular to an interconnect structure and its manufacturing method. Background technique [0002] With the development of the semiconductor industry, when the integration of integrated circuits increases and the surface of the chip cannot provide enough area to make the required interconnection, the multi-layer interconnection design has gradually become a must for many integrated circuits. way of design. [0003] As the semiconductor device shrinks gradually, the overlay window between the upper layer conductive device and the lower layer conductive device below it in the multilayer interconnection structure will also become smaller, so misalignment is prone to occur. When misalignment occurs between the upper layer conductive component and the lower layer conductive component in the multilayer interconnection structure, the upper layer conductive component...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768
CPCH01L21/76802H01L21/76816H01L21/76865
Inventor 李鸿志黄旻暄
Owner MACRONIX INT CO LTD
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