71results about How to "Reduce critical size" patented technology

The invention relates to the field of integrated circuit manufacturing, in particular to a method for decreasing the critical size of a copper-connection groove. In the manufacturing process of a mask of the copper-connection groove, after a traditional process is used for etching to a dielectric layer to form a first groove, a polymer layer is deposited on the surface of a device by the adoption of a plasma deposition process, the first groove is filled with the polymer layer, then plasma etching is conducted, the polymer layer is partially removed, the polymer layer with a certain thickness is reserved on the inner wall of the first groove, so that a second groove which is smaller in size compared with the critical size of an original pattern is formed, afterwards, the second groove is used for etching until a metal through hole area inside a substrate is exposed out of the substrate, and finally the polymer layer left in the groove is removed through the way of wet process cleaning so that the subsequent processes can be continued. According to the technical scheme, in the preparation technology of the copper-connection groove, the critical size of the groove can be decreased, the device performance can be enhanced, meanwhile production cost is low, and therefore the method for decreasing the critical size of the copper-connection groove is suitable for application and popularization.

The invention relates to the field of manufacturing of integrated circuits, in particular to a method for reducing the critical size of a copper interconnection groove. In the mask manufacture process of the copper interconnection groove, the operation of etching is performed to the dielectric layer so as to form a first groove by utilizing the traditional process, thereafter, a silicon nitride film is deposited on the surface of a device through adopting the plasma deposition process and the first groove is filled, then plasma etching is performed, the silicon nitride film is partly removed and the silicon nitride film with a certain thickness is retained on the inner wall of the first groove, so that a first groove with the critical size smaller than that of the original picture is formed, then the operation of etching is performed by utilizing the second groove till a metal through-hole area in the substrate is exposed, and finally the residual silicon nitride film in the groove is removed by adopting wet process cleaning and the follow-up process is performed. Through adopting the technical scheme provided by the invention, in the manufacturing process of copper interconnection groove, the critical size of the groove can be reduced, the performance of the device is improved, and meanwhile the production cost is lower, so that the method facilities application and popularization.

The present invention relates to a high-accuracy wide-range double-layer nano-grating micro displacement detection device. The micro displacement detection device includes a displacement sensing module, a processing unit and a display unit; the displacement sensing module is connected with the display unit through the processing unit; the displacement sensing module comprises double nano-grating layers which can move relative to each other; the double nano-grating layers include a movable nano-grating array and fixed nano-gratings; a plurality of nano-grating regions are spliced to form the movable nano-grating array; certain intervals are left between the plurality of nano-grating regions; the processing unit includes a subdividing circuit; and the subdividing circuit can improve the resolution of the output signals of a photodetector array. The grating period of the micro displacement detection device is smaller than the grating period of an existing micrometer-scale device, and therefore, the micro-displacement detection precision of the gratings is improved; the grating regions of the movable nano-grating array are spliced, so that the range of the micro displacement detection device is wider. The micro displacement detection device has the advantages of compact overall structure, high miniaturization degree and higher practicality.

The invention provides an SONOS (silicon oxide nitride oxide silicon) flash memory device and a compiling method thereof. The SONOS flash memory device comprises a substrate of a cylinder structure and a grid electrode which wraps the middle of the substrate, wherein a source terminal and a drain terminal are respectively arranged at two ends of the substrate, the grid electrode comprises a first silicon gate and a second silicon gate which are parallel, a first oxidation layer is arranged between the first silicon gate and the second silicon gate, and a second oxidation layer arranged on the substrate, a silicon nitride layer arranged on the second oxidation layer and used to store electric charges and a third oxidation layer arranged on the silicon nitride layer are sequentially arranged between the second silicon gate and the substrate. The above structure of the SONOS flash memory device can restrain short channel effects and resist threshold voltage drifts, and simultaneously can effectively reduce the critical size of the SONOS flash memory device. The compiling method of the SONOS flash memory device assists in movement of thermion by adjusting voltage of the grid electrode and the drain terminal, provides sufficient oxidation layer crossing energy to complete compiling, improves compiling efficiency of the SONOS flash memory device, and reduces compiling electric current power consumption.

The invention provides a photoetching-etching technological method of a top select gate cut. A technological step of low temperature oxide (LTO) material deposition is added after photoetching, so that the photoetching critical dimension (PHCD) is reduced equivalently, thereby realizing reduction of the critical dimension of the top select gate cut so as to satisfy the requirement of the miniaturization development of a semiconductor part. Meanwhile, the low temperature oxide (LTO) is used as the deposition material, so that the deposition temperature of the plasma enhanced chemical vapor deposition (PECVD) can be controlled to be about 50 DEG C which is far lower than the bake temperature of 100-120 DEG C of the photo resist material, so that a phenomenon of photo resist material softening in the material deposition can be fully avoided; and by adopting the above-mentioned mode to replace a mode adopting an immersion litho tool, the photoetching critical dimension is reduced economically and stably, thereby further reducing the critical dimension of the top select gate cut.

The technical solution of the present invention discloses an image sensor and a method for forming the same. The method for forming the image sensor includes: providing a semiconductor substrate; forming a first insulating layer on the semiconductor substrate; forming a patterned photoresist layer on the first insulating layer; by using the patterned photoresist layer as a mask, etching the firstinsulating layer to form a metal grid pattern; forming a second insulating layer on the sidewall and the bottom of the metal grid pattern; fully filling the metal grid pattern with a metal layer to form metal grids; and removing the second insulating layer outside the metal grids and a certain thickness of the first insulating layer. The method controls the critical dimension of the metal grids tomeet a corresponding requirement, and further ensures the performance of the image sensor and the yield of devices.

The invention provides a formation method for structure of semi-conductor device, which includes forming several grooves in the base; forming a gate dielectric layer in the grove as an inner liner; filling the grooves with gate materials; re-etching the gate materials to make the top of the grooves be exposed; filling the top of grooves with a first dielectric layer which also covers the surface of the base between two grooves; implementing a first chemical and mechanical grinding techniques to partly eliminate the first dielectric layer, until the surface of the base between two grooves is exposed; using the first dielectric layer, which is used to form the top of the grooves, as an etching mask; and etching the base to form self-aligned contact openings between the grooves by exposing the surface of the base to the air.

The invention relates to a method for manufacturing a vertical SiGe FinFET. The method includes the steps of providing a semiconductor substrate, forming a fin structure on the semiconductor substrate, depositing a first interlayer dielectric layer on the semiconductor substrate, carrying out epitaxy on the fin structure to form a SiGe layer, carrying out H2 high-temperature etching on the fin structure and the SiGe layer for forming vertical side walls, and meanwhile reducing the critical size of the fin structure and the critical size of the SiGe layer. By means of the method, after the fin structure is formed, the SiGe layer is grown on the fin structure in an epitaxy mode, the side wall of the fin structure and the side wall of the SiGe layer are etched with the hydrogen high-temperature etching method to be more vertical, the critical size of the fin structure and the critical size of the SiGe layer are reduced, the integrity of the FET is further improved, and finally the gate-all around is formed. Compared with a plane transistor, the performance of the FET is further improved.

The invention relates to a manufacturing method of a semiconductor device. The manufacturing method comprises the following steps: forming a bit line isolation structure on the side wall of a bit line structure; depositing a contact plug material layer between the bit line isolation structures, wherein the top surface of the contact plug material layer is lower than the top surfaces of the bit line isolation structures; forming a first sacrificial material layer on the surfaces of the contact plug material layer and the bit line isolation structure, patterning the first sacrificial material layer and the contact plug material layer, and forming a gap between the contact plug material layers; and depositing an insulating material in the gap to form contact plugs spaced apart from each other. According to the invention, the consumption of the bit line isolation structure is reduced by utilizing the high etching selection ratio among the contact plug material, the first sacrificial material layer and the bit line isolation structure, so that the thickness of the bit line isolation structure is reduced, and the critical size of the bit line is reduced. And the contact plug material layer is used for providing support for the bit line isolation structure, so that the bit line isolation structure is prevented from collapsing and being separated in the subsequent process.

The invention provides a floating gate flash memory device and a programming method of the floating gate flash memory device. The floating gate flash memory device comprise a substrate of a cylindrical structure, and a source end and a drain end are arranged at the two ends of the substrate; the middle of the substrate is covered with a grid, a gate oxide layer is arranged between the grid and the substrate, and the grid comprises a control gate and a floating gate. According to the programming method of the floating gate flash memory device, movement of hot electrons is assisted by applying bias voltage to provide sufficient energy to cross the gate oxide layer to complete compiling, the compiling efficiency of the flash memory is improved, and power consumption of compiling current is reduced; in addition, the floating gate flash memory device and the programming method of the floating gate flash memory device can effectively reduce the key size of the floating gate flash memory of a parse gate, increase the cell density of a flash memory array and namely increases the storage capacity and density of the flash memory.

The invention discloses a method for improving the uniformity of pattern critical dimensions in a photoetching process. The method comprises the following steps: 1, measuring the influence of various local pattern densities on the pattern critical dimensions in corresponding pattern periods in various pattern periods, and establishing a photoetching process regulation rule according to a measurement result; 2, making local pattern density statistics on local-layer patterns of a designed product layout; 3, regulating photomask critical dimensions corresponding to each pattern of the local-layer patterns according to a local pattern density distribution of the local-layer patterns and the photoetching process regulation rule. According to the method, the influence of changes of the local pattern densities in the layout on the pattern critical dimensions can be eliminated, each pattern critical dimension under the various local pattern densities tend to be the same as a design requirement, and the uniformity of the pattern critical dimensions is improved.

The invention discloses a charge storage structure, a manufacturing method thereof and a nonvolatile memory structure. The charge storage structure is arranged on a dielectric layer of a substrate, and a first undoped charge storage layer and a doped charge storage layer. The first undoped charge storage layer is arranged on the dielectric layer. The doped charge storage layer is arranged on the first undoped charge storage layer.

The invention discloses an etching method of a metal interconnection structure. The method comprises the following steps: covering a photoresist on other areas except a target area of a second hard mask layer through a photoetching process, forming the second hard mask layer on a first hard mask layer, forming the first hard mask layer on a metal layer, and forming the metal layer on a dielectriclayer and a metal connecting line formed in the dielectric layer; trimming the photoresist, so that the photoresist is thinned; carrying out etching to remove the second hard mask layer and the firsthard mask layer in the target area until the metal layer in the target area is exposed; and removing the photoresist. According to the invention, before the hard mask layer of the metal interconnection structure is etched, the hard mask layer is etched, the photoresist is trimmed, the critical size of the photoresist can be reduced in the initial process of subsequent etching, meanwhile, the sizeof the bottom of the photoresist can be reduced, and the roughness of the side wall of the photoresist is reduced, so that the subsequent etched structure has good morphology, and the stability and the manufacturing yield of the device are improved.

The invention provides a method for forming micro-fine patterns on a floating grid, comprising the steps as follows: a multi-crystal silicon layer and a photoresist layer are sequentially formed on a silicon substrate where a floating grid is formed; the photoresist layer is exposed and developed; thermal reflux is carried out to the obtained photoresist patterns; by controlling the reflux temperature and the reflux time, the photoresist patterns with prearranged wire width and spacing are obtained; subsequently, the photoresist patterns with the prearranged wire width and the spacing is transferred to the multi-crystal silicon layer so as to carry out the subsequent preparation. By the method of the invention, patterns with the spacing of 80nm and less than 80nm on the floating grid, which can only be obtained by the more advanced ArF(ASML PAS/1150C) scanner and ArF photoresist, can be obtained only by adopting the KrF(ASML PAS/850c) scanner and thermal reflux KrF photoresist; furthermore, by comparison, the preparation process tolerance is more.

The invention provides a manufacturing method of a trench and a manufacturing method of a memory device. A mask layer comprises an amorphous carbon layer and a DARC layer which are stacked, and the amorphous carbon layer covers a shallow trench isolation layer and a nitride layer; before the mask layer is formed, the nitride layer is not removed, pits are prevented from being formed, the advantage of the high vertical and horizontal etching selection ratio of the amorphous carbon layer is utilized, and the defect that the filling capacity of the amorphous carbon layer is poor is overcome. According to the method, the photoresist layer and the mask layer are etched layer by layer to pattern the photoresist layer and the mask layer, the corresponding opening of the groove is etched by adopting a multi-layer film layer structure formed by overlapping the mask layer and the photoresist layer, and the pattern and size of the opening are sequentially transmitted, so that the resolution and fidelity of the opening pattern are improved, and the accurate control of the key size of the opening pattern is realized. Therefore, the key size of the trench can be accurately controlled, and the key size of the trench can be further reduced. The key size of the trench is reduced, and the channel length of the memory device is correspondingly reduced, so that the effective current and the read window of the memory device can be increased.

The invention provides a programming method for a flash memory device. A flash memory comprises a semiconductor substrate, wherein a source end and a drain end which are arranged in a spaced manner are arranged on the semiconductor substrate; a control gate and a floating gate are arranged above a gap between the source end and the drain end. The programming method for the flash memory device comprises the following steps: when programming operation is performed, respectively applying voltages to the drain end, the floating gate, the control gate and the semiconductor substrate, wherein the range of the voltages applied to the drain end and the floating gate is 2 V to 3 V; the range of the voltages applied to the control gate is 0.7 to 1.0 V; the range of the voltage applied to the semiconductor substrate is 1 V to 1.5 V. According to the method provided by the invention, a channel punch-through effect caused by applying the high voltage to the drain end can be avoided, the critical dimensions of breakdown gate-floating gate flash memories are effectively shortened, and the unit density of an NOR-type or NAND-type flash memory array which takes the breakdown gate-floating gate flash memories as unit devices is increased, so that the storage capacity and the density of the flash memory are improved, and the reliability of the device is improved.

This invention relates to a method for reducing an analytical period of a process including: using a light mask to form a first light resistance layer on part of a basic material and a first material layer on sidewall of the layer, removing the first layer to form a first material layer on part of the basic material at the first stage, carrying out a second process to form a second light resistance layer on the first material layer sidewall, removing the first light resistance layer to form a ditch on the basic material and form a second material layer on sidewall of the ditch, finally, removing the second light resistance layer to form a complex layer of the first and second material layers, so, the first and second layer and contacted together.

The invention provides a trench type field effect transistor structure and a preparation method thereof. The preparation method comprises the steps: providing a substrate of a first doping type, forming an epitaxial layer of the first doping type, forming a trench mask, forming a device trench, forming a gate oxide layer, forming a first conductive layer, forming a body region of a second doping type, forming a source injection region, forming a source electrode of the first doping type based on the trench mask, forming an insulating dielectric layer, enabling the upper surface of the insulating dielectric layer, the upper surface of the gate oxide layer, the upper surface of the source electrode and the upper surface of the body region to be flush, and forming a source electrode. According to the invention, the advantages of a self-alignment process are retained, cell density is effectively increased, a transistor structure and process are improved, the effective electrical extractionof the source electrode and the body region is realized, the key size of a cell is reduced, the electrical extraction mode of the source electrode and the body region is changed while the cell density is improved, the EAS capability of a device is improved, the doping uniformity of the body region is improved, and an extra body region leading-out region does not need to be prepared.