71results about How to "Reduce critical size" patented technology

A method for reducing critical dimension is provided. An exposure process and a develop process are performed on a photoresist layer. An optical trim exposure process is performed between the exposure process and the development process or before the exposure process. The optical trim expsoure process is performed to expose the photoresit layer by using a fully open mask of which the transmission rate is greater than zero. Because of the performance of the optical trim exposure process, the critical dimension of the photoresist layer can be reduced without substantially changing the characteristics of the photoresist layer.

The invention provides a partial-via-first dual-damascene method using a tri-layer resist method forms a first via hole through partial thickness of a dielectric layer, and forms a tri-layer resist structure on the dielectric layer to fill the first via hole with the bottom photoresist layer. A dry development process is performed to transfer a first opening on the top photoresist layer to the middle layer and the bottom photoresist layer, and expose the first via hole again, and remove the top photoresist layer. A dry etching process is then performed to form a second via hole under the first via hole and a trench over the second via hole. Finally a wet striping process is used to remove the remainder of the photoresist layer.

The invention discloses a double-bit flash memory, which comprises a P-type substrate, a first floating gate, a second floating gate, a first control gate and a second control gate, wherein the P-type substrate comprises a source terminal and a drain terminal; the first floating gate, the second floating gate, the first control gate and the second control gate are sequentially located at the upper side and the lower side of the substrate; the first floating gate and the second floating gate are N-type doped polycrystalline silicon; the second control gate is made of P-type polycrystalline silicon; the second control gate is made of N-type polycrystalline silicon; in a programming process, positive drain terminal voltage is exerted on the drain terminal; the source terminal is grounded; the state of electrons stored in the corresponding floating gate is defined to be '1'; if the '1' state is programmed on any control gate, positive grid voltage is exerted on the corresponding control grid, so that an electronic inversion layer is generated on the groove of the substrate; under the accelerating action of the drain terminal voltage, groove electrons obtain enough energy and jump across a potential barrier between a grid oxidation layer and substrate silicon to become hot electrons; the hot electrons are injected into the floating gates to finish programming under the action of the grid voltage. According to the double-bit flash memory, the storage capacity per unit area of a floating gate flash memory is expanded, so that the dimension of the floating gate flash memory can be reduced.

The invention provides a preparation method of a thin film transistor of a flexible electronic device. The method comprises the following steps of: (1) preparing a bendable and stretchable substrate; (2) stretching the substrate, and coating an adhesive on a surface of a stretched rubber substrate; (3) depositing a gate on the substrate; (4) depositing an organic dielectric layer unit on the device which is processed in the step (3); (5) respectively depositing a source unit layer and a drain unit layer on the organic dielectric layer unit; (6) loosening the substrate, releasing loads which are acted on the substrate, and carrying out heat treatment to eliminate an interface stress and a pressure stress of the device; and (7) depositing the organic dielectric layer unit. The invention provides the method for mechanically stretching the substrate, so the channel width of the device is reduced, manufacturing accuracy is improved effectively, and the resolution ratio of the flexible electronic device is improved.

The invention discloses a semiconductor structure forming method and a mask, and the method comprises the steps: providing a substrate which comprises a target layer; forming a core material layer on the substrate, wherein the core material layer comprises a first region and a second region surrounding the first region; ion doping is carried out on the core material layer of the second area, the etching resistance of the core material layer is improved, the core material layer located in the second area serves as an etching resistance layer, and the core material layer located in the first area serves as a core layer; forming a first groove penetrating through at least part of the core material layer in the first region along the first direction, and reserving part of the core material layer in the first region on two sides of the first groove in the second direction; a side wall is formed on the side wall of the first groove, so that a first groove is defined by the side wall; removing the core layer to form a second groove; and etching the target layer below the first groove and the second groove by taking the anti-etching layer and the side wall as masks to form a target pattern. The embodiment of the invention is beneficial to further compressing the pitch between the target patterns.