Formation method for structure of semi-conductor device

Abstract

The invention provides a formation method for structure of semi-conductor device, which includes forming several grooves in the base; forming a gate dielectric layer in the grove as an inner liner; filling the grooves with gate materials; re-etching the gate materials to make the top of the grooves be exposed; filling the top of grooves with a first dielectric layer which also covers the surface of the base between two grooves; implementing a first chemical and mechanical grinding techniques to partly eliminate the first dielectric layer, until the surface of the base between two grooves is exposed; using the first dielectric layer, which is used to form the top of the grooves, as an etching mask; and etching the base to form self-aligned contact openings between the grooves by exposing the surface of the base to the air.

Description

technical field [0001] The present invention relates to a method for forming a semiconductor device structure, and in particular to a method for forming a trench gate metal-oxide-semiconductor field effect transistor (trench gate MOSFET). Background technique [0002] The semiconductor industry continues to improve the integration density of different electronic components. By continuously reducing the minimum component size, more components can be integrated in a given area. For example, the trench gate metal-oxide-semiconductor field effect transistor, which is widely used in power switch devices, utilizes a vertical structure design to increase functional density. It utilizes the backside of the chip as the drain, and manufactures the sources and gates of multiple transistors on the front side of the chip. [0003] However, as the functional density of semiconductor devices continues to increase, the complexity of processing and manufacturing semiconductor devices also i...

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Problems solved by technology

[0003] However, as the functional density of semiconductor devices continues to increase, the complexity of processing and manufacturing semiconductor devices also increases.

For example, due to the limitation of the alignment capability of the conventional lithography exposure equipment, the feature size of the contact structure of the trench gate metal oxide semiconductor field effect transistor cannot be reduced, so the on-resistance of the device cannot be effectively reduced ( onresistance)

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