Manufacturing method of groove and manufacturing method of memory device

Abstract

The invention provides a manufacturing method of a groove and a manufacturing method of a memory device. The manufacturing method comprises the following steps: providing a front-end device; forming an ODL layer; baking the ODL layer to enable the ODL layer to be more compact, and weakening the lateral etching rate; the opening of the corresponding groove formed in the ODL layer does not expand outwards and being not etched laterally, so that the key size of the opening corresponding to the groove is effectively controlled. A photoresist layer, an SHB layer and an ODL layer are etched layer by layer to pattern the photoresist layer, the SHB layer and the ODL layer, a multi-layer film layer structure is adopted to etch corresponding openings of a groove, the patterns and sizes of the openings are transmitted in sequence, the resolution and fidelity of the patterns of the openings are improved, accurate control over the key sizes of the patterns of the openings is achieved, and therefore the key sizes of the groove can be accurately controlled, and the key size of the groove can be further reduced. The key size of the groove is reduced, the channel length of the memory device is correspondingly reduced, a semi-floating gate buried channel with small size and effective vertical morphology is formed, the electrical performance of the semi-floating gate device is improved, and the yield of a memory device wafer is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a groove and a method for manufacturing a storage device. Background technique [0002] Semiconductor memories are used in various electronic fields. Among them, non-volatile memory can save data for a long time in the case of power failure. Semi-floating gate transistors are a mainstream non-volatile memory. The semi-floating gate transistor uses the quantum tunneling effect of the Tunneling Field-Effect Transistor (TFET) and the pn junction diode to replace the traditional silicon oxide erasing window to realize the charge and discharge of the floating gate, which can greatly reduce the transistor The working voltage is higher, and the working speed of the transistor is improved to realize faster data writing and erasing under low voltage, which is convenient to meet the needs of low power consumption of the chip. [0003] The semi-floating ...

AI Technical Summary

Problems solved by technology

It is difficult to further reduce the critical dimension (CD) of the U-shaped trench in the existing semi-floating gate transistor manufacturing process

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