Method for manufacturing vertical SiGe FinFET

Abstract

The invention relates to a method for manufacturing a vertical SiGe FinFET. The method includes the steps of providing a semiconductor substrate, forming a fin structure on the semiconductor substrate, depositing a first interlayer dielectric layer on the semiconductor substrate, carrying out epitaxy on the fin structure to form a SiGe layer, carrying out H2 high-temperature etching on the fin structure and the SiGe layer for forming vertical side walls, and meanwhile reducing the critical size of the fin structure and the critical size of the SiGe layer. By means of the method, after the fin structure is formed, the SiGe layer is grown on the fin structure in an epitaxy mode, the side wall of the fin structure and the side wall of the SiGe layer are etched with the hydrogen high-temperature etching method to be more vertical, the critical size of the fin structure and the critical size of the SiGe layer are reduced, the integrity of the FET is further improved, and finally the gate-all around is formed. Compared with a plane transistor, the performance of the FET is further improved.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular, the invention relates to a method for preparing a vertical SiGe FinFET. Background technique [0002] The improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of integrated circuit devices to increase its speed. Currently, as the semiconductor industry has advanced to nanotechnology process nodes in pursuit of high device density, high performance, and low cost, manufacturing and design challenges have prompted the development of three-dimensional designs such as Fin Field Effect Transistors (FinFETs). [0003] Compared with the existing planar transistors, the FinFET device has more superior performance in terms of channel control and reducing shallow channel effects; the planar gate structure is arranged above the channel, and the gate in the FinFET The fins are arranged around the fins, so static electricity can be controlled from thr...

AI Technical Summary

Problems solved by technology

[0007] Although there are silicon nanowire transistors formed around the gate in the prior art, the channel and the gate are not vertical, which causes a large parasitic capacitance. In the prior art, there are also transistors with a vertical gate and channel. However, its gate is a common gate or tri-gate transistor (tri-gate MOSFET), and its performance and integration are limited. Therefore, it is necessary to improve the method in the prior art on this basis to further improve the performance of the device.

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