Method for reducing critical size of copper interconnection groove

Abstract

The invention relates to the field of manufacturing of integrated circuits, in particular to a method for reducing the critical size of a copper interconnection groove. In the mask manufacture process of the copper interconnection groove, the operation of etching is performed to the dielectric layer so as to form a first groove by utilizing the traditional process, thereafter, a silicon nitride film is deposited on the surface of a device through adopting the plasma deposition process and the first groove is filled, then plasma etching is performed, the silicon nitride film is partly removed and the silicon nitride film with a certain thickness is retained on the inner wall of the first groove, so that a first groove with the critical size smaller than that of the original picture is formed, then the operation of etching is performed by utilizing the second groove till a metal through-hole area in the substrate is exposed, and finally the residual silicon nitride film in the groove is removed by adopting wet process cleaning and the follow-up process is performed. Through adopting the technical scheme provided by the invention, in the manufacturing process of copper interconnection groove, the critical size of the groove can be reduced, the performance of the device is improved, and meanwhile the production cost is lower, so that the method facilities application and popularization.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a method for reducing the key dimension of copper interconnection grooves. Background technique [0002] With the continuous development of technology, the critical dimensions of semiconductor devices are getting smaller and smaller, and the smaller the critical dimensions of the device, the improvement of device performance. Improve device performance. [0003] Figure 1-3 It is a flow chart of the critical dimension manufacturing process of copper interconnect trenches in the field of microelectronics in the prior art, generally including three steps of photolithography, metal hard mask etching and metal trench etching: step a: provide a semiconductor structure, the semiconductor structure includes a substrate 1, and the substrate 1 is sequentially formed with a dielectric layer, a metal hard mask 5 (TiN_MHM) and an oxide layer 6 (OX) from bottom to top, wherein...

AI Technical Summary

Problems solved by technology

However, this invention uses photolithography to form windows and then etch grooves. Due to the poor resolution of traditional photolithography machines, the window pattern after exposure and development is relatively large, which is detrimental to improving device performance. The cost of a new generation of lithography machines is very high, which affects the development of copper interconnection technology

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