Dual-damascene process

Abstract

The invention provides a partial-via-first dual-damascene method using a tri-layer resist method forms a first via hole through partial thickness of a dielectric layer, and forms a tri-layer resist structure on the dielectric layer to fill the first via hole with the bottom photoresist layer. A dry development process is performed to transfer a first opening on the top photoresist layer to the middle layer and the bottom photoresist layer, and expose the first via hole again, and remove the top photoresist layer. A dry etching process is then performed to form a second via hole under the first via hole and a trench over the second via hole. Finally a wet striping process is used to remove the remainder of the photoresist layer.

Description

technical field [0001] The invention relates to a double damascene structure technology, in particular to a double damascene structure technology with partial contact hole priority using three-layer impedance. Background technique [0002] Dual damascene interconnects can provide planarized structures, especially multilayer interconnect structures, which can increase device density and layer count. The application of low dielectric constant (low-k) materials in the semiconductor industry is a trend, especially when copper wires are combined with low dielectric constant materials, it can effectively reduce the resistance-capacitance (RC) delay phenomenon. However, it is difficult to control the etching process of some hole-like low dielectric constant materials, especially in the process of the dual damascene structure. [0003] Dual damascene processes include "via-first" or "trench-first". In the former, the insulating layer is first patterned, and after the formed contac...

AI Technical Summary

Problems solved by technology

However, this method will cause the disadvantages of contact hole offset and metallization polymer is difficult to remove.

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