Method for decreasing critical size of copper-connection groove
A trench, interconnect trench technology, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as high cost, poor resolution, and large window patterns
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[0034] The specific embodiments of the present invention will be further described below in conjunction with the accompanying drawings:
[0035] An embodiment of the present invention will be further described below. Figure 7-12 The flow chart of a preparation method for reducing the key dimensions of copper interconnect trench etching provided by the present invention specifically includes the following steps:
[0036] Step S1. Provide a semiconductor structure. The semiconductor structure includes a substrate 1. A dielectric layer, a metal hard mask 5 (TiN_MHM) and an oxide layer 6 (OX) are sequentially formed on the substrate 1 from bottom to top. The layers include the first dielectric layer 2 (SiCN), the second dielectric layer 3 (SiCOH), and the third dielectric layer 4 (TEOS) from bottom to top; there is a metal via region 9 in the substrate 1, and the metal via region 9 Partially filled with tungsten. In the copper interconnect trench etching process, it is necessary to o...
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