Clock frequency divider

Abstract

The invention discloses a clock frequency divider. The clock frequency divider comprises a control signal production module and a frequency-dividing signal production module; the control signal production module is used for receiving an input clock signal and a frequency-dividing parameter, generating a control signal corresponding to the input clock signal according to the frequency-dividing parameter, and sending the control signal to a frequency-division signal production module; the frequency-dividing signal production module is used for receiving the input clock signal, and generating a sampling clock signal corresponding to the input clock signal according to the received control signal, wherein the starting clock of a clock period corresponding to the sampling clock signal is synchronously changed along the starting clock edge of the clock period corresponding to the input clock signal. The clock frequency divider disclosed by the invention can guarantee the good clock jitteringperformance of the sampling edge corresponding to the sampling clock signal when the sampling clock signal produced by frequency-dividing is used as the sampling clock, and the constraint on the dynamic performance of sampling the high-middle frequency signal through the analog-to-digital converter by the clock jittering performance of the sampling clock edge is greatly weakened.

Description

technical field [0001] The invention relates to the technical field of signal processing, in particular to a clock frequency divider. Background technique [0002] With the rapid development of modern communication systems, higher and higher requirements are placed on the sampling rate and resolution of analog-to-digital converters. As the bandwidth of the sampled signal becomes wider and the frequency of the sampled signal becomes faster and faster, the clock jitter performance of the sampling clock has a greater impact on the dynamic performance of the analog-to-digital converter (such as the signal-to-noise ratio). Therefore , the jitter performance of the sampling clock restricts the improvement of the signal-to-noise ratio of the analog-to-digital converter to a large extent. [0003] In the prior art, for the convenience of system application, a clock signal of the same frequency is often sent to each circuit module of the system. Specifically, the internal sampling ...

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Problems solved by technology

[0004] The technical problem to be solved by the present invention is to overcome the traditional CMOS clock frequency divider used in the prior art to divide the frequency of the clock signal, and the clock jitter performance of the output clock is relatively poor, which seriously restricts the high-speed, high-speed The defect of improving the dynamic performance when the precision analog-to-digital converter samples high-frequency signals and intermediate-frequency signals, the purpose is to provide a clock divider

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