Parameter modular implementation method and system for preventing frequent reset of BMC

The technology of a parameter module and an implementation method is applied in the field of a parameter module implementation method and a system to prevent frequent resets of the BMC, and can solve problems such as lowering the reliability design of the server, the server cannot work normally, and the BMC hangs, etc., so as to increase portability, Avoid hanging and improve reliability

Inactive Publication Date: 2018-08-07
ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This implementation method can realize the BMC logic reset function in a normal test environment, but in an extreme test environment, such as frequent resets of BMC_RSTBTN#, it will cause the BMC to hang up due to frequent response to the reset logic, and thus cannot be resurrected, which will cause the server Can not work normally
This seriously reduces the reliability design of the server

Method used

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  • Parameter modular implementation method and system for preventing frequent reset of BMC
  • Parameter modular implementation method and system for preventing frequent reset of BMC

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Embodiment Construction

[0028] The content of the present invention is described in more detail below:

[0029] figure 1 It is a structural diagram of controlling the BMC reset button based on CPLD-FPGA. "RST_BTN#" is a button input signal, corresponding to the BMC reset request button in the server, and this signal is used as an input signal of CPLD-FPGA through wiring; "CPLD-FPGA "is the logic control chip in the server, and the "BMC button reset control module" is implemented in the chip through Verilog hardware description language programming; "SRST#" is the reset input signal on the server, which is connected to the CPLD-FPGA output terminal through wiring , to realize the reset request of BMC.

[0030] Emphasis of the present invention is the button reset control module design based on CPLD-FPGA realization, and specific work flow is: at first monitor the falling edge of " RST_BTN# " reset signal in real time by high-speed clock; When CPLD-FPGA detects " RST_BTN# " reset request CPLD-FPGA fi...

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Abstract

The invention provides a parameter modular implementation method and system for preventing frequent reset of BMC, and belongs to the field of server BMC reset button application. The method is based on CPLD-FPGA to achieve the design of a BMC button reset control module, a BMC reset signal is output for effective duration through logic control, the suspension of the BMC caused by frequent reset can be avoided through logic control, and the reliability design of a server is improved. A modular and parametric design improves the flexibility and portability of the BMC button reset control module.

Description

technical field [0001] The invention relates to a server BMC reset button application technology, in particular to a method and system for implementing parameter modularization to prevent frequent BMC resets. Background technique [0002] In the server system, the power-on and power-off sequence control, LED indicator control, communication control, key detection and judgment, power-down detection and fan control of the entire server are usually controlled by the CPLD-FPGA chip. Functions such as local and remote diagnosis, console support and configuration management control are realized through BMC. Both are important components of a server system. [0003] When power-on for the first time or when BMC reset is requested by the external key (BMC_RSTBTN#), the entire BMC chip function will be reset, including PCIe communication and VGA display. The reset function implemented by the first power-on is generated by the chip logic, and the BMC reset is realized through a butto...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F1/24
CPCG06F1/24
Inventor 季冬冬
Owner ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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