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Implementation method for clipping region segmentation technology for parallel drawing in GPU

A technology of cropping area and implementation method, which is applied in image analysis, 2D image generation, details involving image processing hardware, etc.

Active Publication Date: 2018-08-10
CHANGSHA JINGJIA MICROELECTRONICS
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  • Abstract
  • Description
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  • Application Information

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Problems solved by technology

[0002] The GPU graphics drawing pipeline includes processes such as command processing, vertex acquisition, vertex processing, primitive assembly, clipping, rasterization, fragment processing, and pixel processing. These processes have sequential requirements, and parallel drawing is a way to improve GPU performance. Important processing method, but due to sequential requirements, it cannot be parallelized by ordinary drawing commands or vertices

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  • Implementation method for clipping region segmentation technology for parallel drawing in GPU
  • Implementation method for clipping region segmentation technology for parallel drawing in GPU
  • Implementation method for clipping region segmentation technology for parallel drawing in GPU

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Embodiment Construction

[0014] The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

[0015] Such as figure 1 As shown, when the clipping area is divided in the X direction or the Y direction, the range of the drawing area determined by the clipping equation is used to divide the drawing area into n disjoint areas using different clipping equations, n is a natural number, and each clipping module is configured according to The parameters of each perform cutting, and the configuration parameters of each cutting module are different: use the equation Indicates that the upper and lower clipping planes in the Y direction are expressed by the equation Indicates that the entire drawing area is divided into n disjoint areas: the value of the clipping plane parameter configuration of the i-th clipping module is: when the X direction is selected, take When splitting in the Y direction is selected Among them, i∈[1, n] is ...

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Abstract

The invention discloses an implementation method for the clipping region segmentation technology for parallel drawing in a GPU, and the method comprises the steps: changing a fixed clipping plane equation into a parameter configuration equation, and dividing a whole drawing region into a plurality of areas which are not intersected. The operations of the clipped areas are respectively operated soas to achieve the parallel drawing, and to improve the drawing efficiency. The implementation method achieves the dividing of the clipping region after the commanding processing, top point obtaining,top point processing and primitive assembly, enables the same primitive to be distributed to the plurality of clipped areas for clipping at the same time, and enables an original clipping module to become a plurality of clipping modules for the simultaneous clipping.

Description

technical field [0001] The present invention mainly relates to the field of GPU design, in particular to the field of realization of GPU parallel drawing. Background technique [0002] The GPU graphics drawing pipeline includes processes such as command processing, vertex acquisition, vertex processing, primitive assembly, clipping, rasterization, fragment processing, and pixel processing. These processes have sequential requirements, and parallel drawing is a way to improve GPU performance. Important processing method, but due to sequential requirements, it cannot be parallelized by ordinary drawing commands or vertices. [0003] For example, the parallel rendering technology based on block rendering requires the block operation of primitives after clipping, and the technology of performing block and drawing separately. Contents of the invention [0004] The problem to be solved by the present invention is to provide a method for implementing the clipping area segmentati...

Claims

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Application Information

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IPC IPC(8): G06T1/20G06T7/11G06T11/00
CPCG06T1/20G06T7/11G06T11/00G06T2200/28
Inventor 陈宝民焦永
Owner CHANGSHA JINGJIA MICROELECTRONICS
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