A kind of manufacturing method of silicon epitaxial wafer for coolmos

A manufacturing method and technology of silicon epitaxial wafers, which are applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as circuit pattern damage, slow polishing rate, low production efficiency, etc., to reduce impact and optimize surface quality. , the effect of eliminating the damage layer

Active Publication Date: 2020-08-04
NANJING GUOSHENG ELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The conventional method is to inject HCl gas for gas polishing. In the existing method, if the HCl polishing rate is too slow, the production efficiency will be low, and if the polishing rate is too fast, the photoetched circuit pattern will be damaged.

Method used

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  • A kind of manufacturing method of silicon epitaxial wafer for coolmos
  • A kind of manufacturing method of silicon epitaxial wafer for coolmos
  • A kind of manufacturing method of silicon epitaxial wafer for coolmos

Examples

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Effect test

Embodiment 1

[0032] A method for manufacturing a silicon epitaxial wafer for COOLMOS of the present embodiment comprises the following steps:

[0033] The equipment used in the present invention is the American ASM E2000 silicon epitaxial growth equipment, such as figure 2 As shown, the ASM E2000 silicon epitaxial growth equipment includes a pedestal 1, a pedestal ring 2 located on the pedestal 1, a central thermocouple 3 set in the pedestal ring 2, and also includes a front-end thermocouple 4, a rear-end thermocouple 5. Side-end thermocouple 6, side-end auxiliary thermocouple 7. The base is a high-purity graphite base and serves as an infrared heating body, and the purity of the main carrier gas H2 is above 99.9999%.

[0034] Cleaning of the reaction chamber: The quartz bell jar and the quartz parts used in the reaction chamber must be carefully cleaned before epitaxy, and the deposition residue on the inner wall of the quartz bell jar and the quartz parts must be completely removed.

...

Embodiment 2

[0043] The first four steps are described in the first embodiment.

[0044] Step 5: Gas etching is used to polish the surface of the silicon wafer. HCl gas with a flow rate of 1slm and H2 with a flow rate of 60slm are introduced for polishing. The polishing rate is 0.15μm / min, the polishing time is 3min, and the polishing thickness is 0.45μm. H in the fourth step 2 Bake at same temperature.

[0045] Step 6: After polishing, the temperature rises to 1190°C, and at the same time, the dopant source is expelled, and the expelled flow rate is determined according to the resistivity requirement of the epitaxial layer

[0046] Step 7: Epitaxial growth to control the thickness of the epitaxial layer: feed TCS, H2 and doping sources into the reaction chamber at the same time for epitaxial growth, feed TCS with a flow rate of 8g / min and H2 with a flow rate of 60slm, and the growth rate is 2.5μm / min . The flow rate of the doping source is determined according to the requirement of the...

Embodiment 3

[0048] The first four steps are described in the first embodiment.

[0049] The fifth step: gas corrosion to polish the surface of the silicon wafer, pass HCl gas with a flow rate of 0.8slm and H2 with a flow rate of 80slm for polishing, the polishing rate is 0.12μm / min, the polishing time is 2min, the polishing thickness is 0.24μm, and the polishing temperature and H in the fourth step 2 Bake at same temperature.

[0050] Step 6: After polishing, the temperature rises to 1170°C, and at the same time, the dopant source is expelled, and the expelled flow rate is determined according to the resistivity requirement of the epitaxial layer

[0051] Step 7: Epitaxial growth to control the thickness of the epitaxial layer: feed TCS, H2 and dopant sources into the reaction chamber at the same time for epitaxial growth, feed TCS at a flow rate of 6g / min and H2 at a flow rate of 80slm, and the growth rate is 2μm / min. The flow rate of the doping source is determined according to the re...

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Abstract

The invention relates to a manufacturing method of a silicon epitaxial wafer for a COOLMOS. The technical process lies in that single normal-pressure silicon epitaxial equipment is employed, appropriate H2 flow, temperature and time are selected to perform baking on a substrate silicon wafer, a natural oxide layer on a surface is removed, and the quality of an epitaxial front surface is ensured; and gas polishing is performed on a surface of the substrate by employing low flow HCL and low polishing rate, and damage to a surface of a silicon wafer caused by stages of photoetching and injectionis reduced. In epitaxial growth, SiHCl3 is used as a silicon source, relatively high temperature is employed, meanwhile, the main H2 flow is increased to reduce the growth rate, and an epitaxial layerconforming to the requirement of a COOLMOS device is grown.

Description

technical field [0001] The invention relates to a silicon epitaxial wafer, especially a method for manufacturing a silicon epitaxial wafer for COOLMOS. Background technique [0002] When making COOLMOS devices by combining multiple epitaxy and ion implantation, since the silicon wafer will be subjected to an ion implantation and photolithography after each epitaxy, it will often cause slight damage to the surface of the silicon wafer. Handling is key. The conventional method is to inject HCl gas for gas polishing. In the existing method, if the HCl polishing rate is too slow, the production efficiency will be low, and if the polishing rate is too fast, the photoetched circuit pattern will be damaged. At the same time, after the last multiple epitaxy, the lithography mark will appear certain distortion, which will affect the lithography machine alignment, so the control of pattern distortion is also the key. [0003] In summary, it is necessary to design a manufacturing met...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/02
CPCH01L21/02381H01L21/02658
Inventor 刘勇邓雪华孙健杨帆任凯石卓亚骆红
Owner NANJING GUOSHENG ELECTRONICS
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