Test method and system for testing internal eye diagram of chip

Abstract

The invention discloses a test method and system for testing an internal eye diagram of a chip. The method comprises the following steps: S1, erecting a test platform and inputting a reference voltagesignal and a clock signal at a to-be-tested chip receiving end to obtain a sampling point; S2, adjusting a clock signal phase and a reference voltage signal to change the location of the sampling point, and testing the obtained sampling point to obtain a boundary sampling point with an error code; S3, repeated the previous step to obtain a plurality of boundary sampling points, connecting the boundary sampling points to form a boundary contour of an internal signal of the chip so as to obtain eye height and eye width data and a signal simulation eye diagram; and S4, compensating the referencevoltage signal and the clock signal and determining the compensated eye height and eye width data to obtain a final internal signal eye diagram of the chip. According to the invention, with internalsimulation testing, parameter adjustment becomes convenient; the consistency of the testing result and the internal actual signal of the chip is ensured; and the precision of the chip signal eye diagram result is improved.

Description

technical field [0001] The invention relates to the field of chip testing, in particular to a testing method and system for testing an internal signal eye diagram of a chip. Background technique [0002] For chip testing for high-speed signal processing, there is usually De-emphasis at the sending end, and DFE and CTLE at the receiving end. The two work together to ensure that the eye diagram of the signal at the receiving end meets the requirements. The traditional high-speed signal test method is to connect the fixture test at the receiving end, or solder or spot test at the receiving end, and then use an oscilloscope to analyze the eye diagram. [0003] The above test method has two disadvantages: First, the signal is tested outside the chip at the receiving end, and it is necessary to simulate the effect of DFE and CTLE on the signal at the receiving end of the chip to obtain the final eye diagram. Generally, the DFE and CTLE are simulated inside the oscilloscope. CTLE ...

AI Technical Summary

Problems solved by technology

[0005] The present invention proposes a test method and system for testing the internal signal eye diagram of a chip, which is used to solve the problem that there is an error between the results obtained by the existing chip test method and the test results and the actual signal inside the chip, resulting in inaccurate test results

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