Delay-locked loop with wide frequency input range

Abstract

The invention discloses a delay-locked loop with a wide frequency input range, comprising a phase detection module, a delay module, a control module, an adjustment module and a selection module; wherein two input ports of the phase detection module are connected with a reference clock and a feedback clock respectively, a phase state output port of the phase detection module is connected with an input port of the control module; an input port of the delay module is connected with the reference clock, input ports of the selection module are respectively connected with output ports of the controlmodule and the delay module, the delay module comprises at least one delay chain; an output port of the selection module outputs a selected clock, two input ports of the adjustment module are respectively connected with a counting clock and the reference clock, and an output port of the adjustment module is connected with the delay module. According to the delay-locked loop with the wide frequency input range in the invention, the delay chains can be selected automatically from the inside, so that the delay-locked loop can operate normally all the time, thereby widening the operating frequency range of the delay-locked loop.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a delay-locked loop with a wide frequency input range. Background technique [0002] With the development of CMOS integrated circuit technology, clock circuits play a very important role in both digital and analog integrated circuit design. However, PLL (Phasel Locked Loop) phase-locked loops are basically designed using analog circuits, and the circuit noise problem is relatively large, and the circuit design is difficult and the reusability is poor. The DLL (Delay Locked Loop) delay-locked loop, especially the all-digital DLL circuit, is more and more widely used because it is completed based on digital logic, the circuit noise performance is good, and the circuit has strong reusability. [0003] Moreover, in some circuit designs, not only strict requirements are placed on the clock frequency, but also the phase of the clock is also very concerned. For example, in TDC...

AI Technical Summary

Problems solved by technology

For all-digital DLLs, the operating frequency range of the DLL is limited due to the limitation of the number of delay units, resulting in poor reusability of the DLL.

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