A High Speed ​​Level Shifter Circuit with Adjustable Duty Cycle

Abstract

The invention discloses a high-speed level shifter circuit with an adjustable duty ratio. The circuit comprises a first transistor MN1, a second transistor MN2, a third transistor LN1, a fourth transistor LN2, a fifth transistor N0, a sixth transistor LP1, a seventh transistor LP2, an eighth transistor LP3, a ninth transistor LP4, a tenth transistor MP1, an eleventh transistor MP2, a first phase inverter, a second phase inverter, a third phase inverter, a fourth phase inverter, a fifth phase inverter, a sixth phase inverter, a seventh phase inverter, an eighth phase inverter and a NOR gate; the number accessing to the circuit P tube is controlled through NOR logic, thereby adjusting the output waveform duty ratio. The level shifter disclosed by the invention can convert an input signal ofthe low-voltage level into an output signal of the high-voltage level without using a high-voltage transistor, the voltage conversion range is broadened, and the signal transmission rate is improved.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to the field of integrated circuit I / O design, and in particular to a high-speed level shifter circuit with adjustable duty cycle. Background technique [0002] VLSI technology enables complex system-on-chip (SoC) designs that integrate analog and digital circuits, as well as different parts such as passive components, into a single chip. In such SoCs, different parts of the chip need to run at different voltages to achieve the best speed / power ratio, so communication between different parts of the chip requires level shifters to convert logic signals from one voltage level shift to another voltage level. With the continuous improvement of the scale and power consumption of integrated circuits, realizing the optimal balance between performance and power consumption according to real-time load has become an important factor to be considered in circuit design, which puts forw...

AI Technical Summary

Problems solved by technology

The traditional level shifter performs conversion at a specific voltage, and the voltage conversion range is narrow

In addition, under different voltage domains, due to the fixed size of the MOS tube, the output duty cycle cannot be changed, which will affect the signal transmission speed. Turning off early to improve the output duty cycle will not only cause a larger short-circuit current between vdda and vss, but also narrow applicability

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