A kind of sram memory

Abstract

The invention discloses an SRAM memory, which comprises a tracking clock generator and two SRAM arrays symmetrically distributed, a tracking row is arranged on the upper part of each SRAM array, and a tracking column is arranged on the outer side, and a tracking row is arranged above each SRAM array. There is a timing tracking unit dummy cell on the outside of the row, and a dummy SA sense amplifier is arranged below each SRAM array. The output terminal INTERNAL-CLK of the tracking clock generator passes through two tracking word lines passing through the tracking row and on both sides respectively. The timing tracking unit dummy cell is connected, and each timing tracking unit dummy cell is connected to the dummy SA sense amplifier through a tracking bit line passing through the tracking column, and the output terminal of the dummy SA sense amplifier is connected to the tracking clock generator through a decision device The input end of the device also includes a PBTI protection circuit based on a dummy SA sense amplifier. The invention can not only reduce the failure probability of the memory due to the tracking path, increase the accuracy of the tracking operation, but also eliminate the influence of the PBTI effect and improve the reliability of the circuit.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to an SRAM memory. Background technique [0002] In recent years, Static Random Access Memory (SRAM) has been widely used because of its high speed and simple system design. The SRAM cell is typically a 6-transistor cell with two inverters connected to form a latch. The laterally cross-connected inverters will maintain the stored data as long as power continues to be supplied to the device, rather than needing to be refreshed to retain the data. [0003] SRAM memory cells have a word line and two bit lines in opposite phases. The two bit lines are connected to the small signal differential sense amplifier. When the SRAM reads, both bit lines are initially precharged high. When the word line voltage rises to the activation level, the SRAM storage unit connected to the word line is selected, and its transfer transistor is activated to connect the bit line to the storage unit. A...

AI Technical Summary

Problems solved by technology

The failure of the traditional SRAM storage unit can be repaired through the redundancy mechanism. If the tracking mechanism fails, there is no remedy

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