Storage component testing method and device

Abstract

The invention discloses a storage component testing method. According to the method, configuration information of a storage component is acquired, and storage component access address configuration isdetermined according to the configuration information and preset address access rules; read-write processing is performed on the storage component according to the storage component access address configuration and preset storage component read-write rules; and a result obtained after read-write processing of the storage component is acquired, and the position of an error in the storage componentis determined according to preset detection rules. The invention furthermore discloses a storage component testing device.

Description

technical field [0001] The invention relates to a multi-chip packaging and testing technology, in particular to a storage component testing method and device. Background technique [0002] In the existing multi-chip package dynamic random access memory (DRAM, Dynamic Random Access Memory) built-in self-test method, the address traversal order, read and write operation order, address space, etc. cannot be flexibly configured, and the test vectors that can be combined It is very simple and cannot provide sufficient coverage; for example, Synopsis's double-rate synchronous dynamic random access memory physical layer (DDR PHY, Double Data Rate synchronous dynamic random access memory PHYsical layer), which provides DRAM built-in self-test (BIST, Build In Self-Test), the address space of a test is only 2Mbit, and only 8 data lines (DQ) can be tested each time; for the current 1Gbit or larger DRAM, the DRAM with a bit width of 32 bits needs to be configured multiple times ; Moreo...

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Problems solved by technology

[0002] In the existing multi-chip package dynamic random access memory (DRAM, Dynamic Random Access Memory) built-in self-test method, the address traversal order, read and write operation order, address space, etc. cannot be flexibly configured, and the test vectors that can be combined It is very simple and cannot provide sufficient coverage; for example, Synopsis's double-rate synchronous dynamic random access memory physical layer (DDR PHY, Double Data Rate synchronous dynamic random access memory PHYsical layer), which provides DRAM built-in self-test (BIST, Build In Self-Test), the address space of a test is only 2Mbit, and only 8 data lines (DQ) can be tested each time; for the current 1Gbit or larger DRAM, the DRAM with a bit width of 32 bits needs to be configured multiple times ; Moreover, the read and write sequence of DDR PHY can only provide the operation sequence of increasing the Y address direction and writing first and then reading, and the test method is relatively simple

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