Test method and circuit for detecting memory fault

Abstract

The invention provides a test method and circuit for detecting a memory fault. The test method comprises the following steps: sequentially performing W0 operation on each address from a low address toa high address or from a high address to a low address; and sequentially performing W0 operation, R0 operation, R0 operation, W1 operation and R1 operation on each address of a memory from a high address to a low address; sequentially performing R1 operation, W0 operation, W0 operation, and R0 operation on each address of the memory from a low address to a high address; sequentially performing R0operation, W1 operation, W1 operation and R1 operation on each address of the memory from a high address to a low address; sequentially performing W1 operation, R1 operation, W0 operation and R0 operation on each address of the memory from a high address to a low address; and sequentially performing R0 operation on each address of the memory from a low address to a high address or from a high address to a low address. The test method can quickly test the disturb fault, the stuck-open fault and the conventional fault of the memory, and the test time is short.

Description

technical field [0001] The invention relates to the field of semiconductor devices, in particular to a test method and a test circuit for detecting memory faults. Background technique [0002] As the CMOS process size is reduced to 40nm or even lower, and the design of SRAM (Static Random Access Memory) cells must follow some established design rules and characteristics that meet the design density requirements, etc., the design of SRAM cells has become more and more complicated. It's getting harder. More importantly, as the capacity of the memory becomes larger and the integration level becomes higher and higher, the transistors inside the memory become denser, as well as the slight fluctuation of device parameters and some changes in characteristics, etc., it is inevitable The performance of the SRAM is affected, and the problem of interference faults in the memory is becoming more and more prominent. [0003] At low voltage, the probability of interference failure of th...

AI Technical Summary

Problems solved by technology

More importantly, as the capacity of the memory becomes larger and the integration level becomes higher and higher, the transistors inside the memory become denser, as well as the slight fluctuation of device parameters and some changes in characteristics, etc., it is inevitable Affecting the performance of SRAM, the problem of interference faults in memory has become increasingly prominent

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