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Transistor and method of making the same

A manufacturing method and transistor technology, applied in semiconductor devices, nanotechnology for materials and surface science, electrical components, etc., to reduce parasitic capacitance and achieve shading effects

Active Publication Date: 2021-05-14
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At present, the physical gate length of field effect transistors is close to 20nm, and the gate dielectric is only a few oxygen atoms thick. There are some difficulties in improving performance by reducing the size of traditional field effect transistors.

Method used

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  • Transistor and method of making the same
  • Transistor and method of making the same
  • Transistor and method of making the same

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Embodiment Construction

[0045] The transistor of the present invention and its manufacturing method will be described in more detail below in conjunction with schematic diagrams, wherein a preferred embodiment of the present invention is represented, and it should be understood that those skilled in the art can modify the present invention described here, while still realizing the advantages of the present invention Effect. Therefore, the following description should be understood as the broad knowledge of those skilled in the art, but not as a limitation of the present invention.

[0046] In the following paragraphs the invention is described more specifically by way of example with reference to the accompanying drawings. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrat...

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PUM

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Abstract

The present invention discloses a transistor and a manufacturing method thereof. The transistor includes a semiconductor substrate; a stacked structure on the semiconductor substrate, the stacked structure includes a first stacked layer and a second stacked layer alternately stacked, the first stacked layer a stacked layer protruding from the second stacked layer to form an opening on the outside of the stacked structure; a film sidewall located in the opening, the film sidewall located on the sidewall of the second stacked layer and the first stacked layer The surface of the layer; the gate structure on the stacked structure. As a result, a film sidewall is formed in the opening caused by the first stacked layer protruding from the second stacked layer, which realizes the shielding of the opening, thereby reducing the parasitic between the gate and the source / drain. capacitance.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a transistor and a manufacturing method thereof. Background technique [0002] It has always been the goal pursued by the development of microelectronics industry to increase the working speed and integration of chips and reduce the power consumption density of chips by reducing the size of transistors. In the past forty years, the development of microelectronics industry has been following Moore's Law. At present, the physical gate length of field effect transistors is close to 20nm, and the gate dielectric is only a few oxygen atoms thick. It is already facing some difficulties to reduce the size of traditional field effect transistors to improve performance. [0003] Nanowire Field Effect Transistor (NWFET, Nano-Wire MOSFET) has become a better trial solution. On the one hand, the channel thickness and width in NWFETs are smaller, making the gate closer to various par...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/423H01L21/28B82Y30/00B82Y40/00
CPCB82Y30/00B82Y40/00H01L29/401H01L29/42356
Inventor 张海洋刘少雄
Owner SEMICON MFG INT (SHANGHAI) CORP