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Watchdog circuit implementation method and system

An implementation method and system implementation technology, applied in the direction of response error generation, electrical digital data processing, instruments, etc., can solve problems such as increasing system overhead, system abnormal reset, and reducing system performance, so as to improve work performance and reduce The probability of abnormal reset and the effect of reducing overhead

Inactive Publication Date: 2018-11-06
烽火超微信息科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The disadvantage of the hardware watchdog is: the system needs to send a high-low level conversion signal to the timer according to a certain frequency during the working period, so as to realize the dog feeding function; however, the timer of the hardware watchdog requires 2 times of dog feeding The interval time (that is, the interval between sending two signals) is less than 1.6s, which will cause the system to frequently send level-changing signals to the timer (send once within 1.6s), which not only increases the overhead of the system, but also reduces the The working performance of the system is affected, and when the system resources are not enough, it often occurs that the system resets abnormally due to the untimely feeding of the dog.

Method used

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  • Watchdog circuit implementation method and system

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Experimental program
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Embodiment 1

[0035] Before S1, the following steps are also included: the CPU sets the dog feeding cycle to the CPLD, and the dog feeding cycle can be flexibly set and adjusted according to needs in practical applications.

Embodiment 2

[0037] Before S1, the following steps are also included: before the CPU initialization is completed, the CPLD feeds the hardware watchdog chip, and after the CPU initialization is completed, go to S1. The principle of CPLD feeding the hardware watchdog chip is the same as that of S1, specifically: CPLD sends high and low level conversion signals to the watchdog chip, and the sending frequency of the conversion signal matches the watchdog chip. After the watchdog chip receives a change signal, it judges whether it receives another change signal with a different level within the specified period. If it is, it means that the CPLD is normal and continues to work. Otherwise, it means that the CPLD is abnormal and returns a reset signal to the CPLD.

Embodiment 3

[0039] During the dog feeding period, the CPLD in S1 receives the high and low level conversion signal sent by the CPU of the system. The judgment standard is: after the CPLD receives the conversion signal once, it receives a different level conversion again during the dog feeding period. For example, the signal is high level this time and low level last time, or low level this time and high level last time.

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Abstract

The invention discloses a watchdog circuit implementation method and system, and relates to the field of embedded system design. The method comprises the steps that S1, an CPLD judges whether a conversion signal of a high level and a low level sent by a CPU of a system is received in a dog feeding period or not, and if yes, performing operation of going to the step S2, otherwise, performing operation of going to the step S3; S2, the CPLD sends a dog feeding signal to a watchdog chip, wherein the sending frequency of the dog feeding signal is matched with the watchdog chip; and S3, the CPLD sends a working exception signal to the watchdog chip, the watchdog chip returns a reset signal to the CPLD after receiving the working exception signal, and the CPLD returns the reset signal to the CPUof the system. When the watchdog circuit works, the overhead of the system and the probability of exceptional reset can be reduced, so that the working performance of the system is improved.

Description

technical field [0001] The invention relates to the field of embedded system design, in particular to a method and system for realizing a watchdog circuit. Background technique [0002] The watchdog circuit is a chip circuit that resets the system when the timer overflows. The watchdog circuit has the highest priority in program interruption. The watchdog circuit is divided into hardware watchdog and software watchdog: [0003] The hardware watchdog uses a timer chip circuit, the output terminal of the timer is connected to the reset terminal of the circuit, and the reset terminal is connected to the CPU of the system. The working method of the hardware watchdog is: if the system clears the timer within the specified time (commonly known as "feeding the dog"), the timer will not overflow, and the timer will not generate a reset signal to cause the system to reset (that is, restart the system ); if the system does not feed the timer within the specified time, the timer will...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/07G06F1/24
CPCG06F1/24G06F11/0757
Inventor 刘丽
Owner 烽火超微信息科技有限公司