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Buffer-level device capable of interfacing to a serial peripheral interface bus

A buffer level, buffer module technology, applied in the direction of logic circuit connection/interface layout, logic circuit interface device, instrument, etc., can solve the problem of short-term consumption

Active Publication Date: 2021-05-07
STMICROELECTRONICS (ROUSSET) SAS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This creates a brief drain of extremely high current

Method used

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  • Buffer-level device capable of interfacing to a serial peripheral interface bus
  • Buffer-level device capable of interfacing to a serial peripheral interface bus
  • Buffer-level device capable of interfacing to a serial peripheral interface bus

Examples

Experimental program
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Embodiment Construction

[0046] figure 2 An example of a buffer level device DIS comprising a data input ED, a clock input ECL and a data output SD is shown.

[0047] The processor MTR is coupled to inputs ED, ECL and output SD and comprises a trigger signal generator LZGEN, a first flip-flop ACDFF and a first buffer block ACBUF, and a second flip-flop DCDFF and a second buffer block DCBUF.

[0048] A data signal DAT (for example, data resulting from a read operation in a memory plane of the EEPROM memory) is transmitted to a data input ED, and a clock signal CLK is transmitted to a clock input ECL.

[0049] The clock signal CLK comes, for example, from a master on the SPI bus and is a signal with a staircase oscillation in a conventional and known manner. The high and low levels of the clock signal are called polarity, and the period of the clock signal is called the clock period. The transition from low polarity to high polarity (and vice versa) is called a rising edge (and a falling edge).

[0...

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Abstract

The present disclosure provides a buffer level device capable of connecting to a serial peripheral interface bus. In some embodiments, a buffer stage apparatus includes a data input for receiving a data signal, a clock input for receiving a clock signal, a data output, and a data output configured to transmit data from Processor for the data of the data signal. The processor includes a first buffer module configured to transfer each data to the data output synchronously with the first edge of the clock signal during the first half of the clock cycle and configured to hold the data during the second half of the clock cycle Second buffer block at data output.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from French Patent Application No. 1753971 filed May 5, 2017, which is hereby incorporated by reference. technical field [0003] Embodiments of the present invention relate to buffer level devices that can be connected to a serial peripheral interface bus. Background technique [0004] The two main characteristics of a conventional synchronous output buffer stage are the switching time (that is, the time it takes for the buffer's logic to transfer to the output the data present at the input when a clock edge occurs) and the The amount of current to be distributed at the input of a circuit to which it is connected (a plurality of circuits connected to which the output can drive (often referred to using the term "fan-out"). [0005] It is preferable that the switching time is as short as possible and the "fan-out" is high, especially in "transistor-transistor" logic (TTL) systems or NM...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/40G06F13/42H03K19/0175
CPCG06F13/4022G06F13/4072G06F13/4291H03K19/017509H03K19/018521G06F13/385H03K19/0002Y02D10/00G06F13/1673G06F13/1689G06F13/4059H03K19/01728
Inventor F·塔耶C·阿梅兹亚内埃尔阿萨尼
Owner STMICROELECTRONICS (ROUSSET) SAS