A Reconfigurable CNN High Concurrency Convolution Accelerator

Abstract

The present invention provides a reconfigurable CNN high-concurrency convolution accelerator, including: a weight address generation unit, which generates the address of the convolution kernel data in the cache; a result address generation unit, which generates the address of the result data in the cache; The computing unit can reconstruct the computing array into two kinds of multiply-accumulate tree circuits with different granularities; the feature map address generation unit can generate the address of the feature map data in the cache; the main controller can generate and reset the accumulator synchronously with the address Signal, gates the corresponding circuit in the reconfigurable computing unit, and generates an interrupt signal for the end of the entire operation; the storage exchange unit converts the effective feature map read address and weight read address into a read operation for the storage unit, and converts the effective result Writing addresses and data translates to write operations to memory cells. Beneficial effects: the control part is simplified, the parallelism of multi-channel two-dimensional convolution operation and the efficiency of storage access are greatly improved, and the occupied resources are reduced.

Description

technical field [0001] The invention relates to a hardware architecture for accelerating convolution operations, in particular to a reconfigurable CNN high-concurrency convolution accelerator. Background technique [0002] On the one hand, with the continuous improvement of semiconductor process technology, the computing performance of the processor has been further improved, on the other hand, the explosive development of the mobile Internet, the massive data generated can be easily obtained. Under this background, the neural network has obtained a new development, especially in the fields of image recognition, speech recognition and other key breakthroughs. The convolutional layer in the convolutional neural network belongs to the multi-channel two-dimensional convolution operation, and the size of the input feature map is set to S f ×S f ×C f , the convolution kernel size is S k ×S k ×C f ×C k , the output size is S o ×S o ×C o , the convolution stride is S. th...

AI Technical Summary

Problems solved by technology

[0004] At present, the acceleration of neural networks is highly dependent on Nvidia's GPU accelerator card, and its shortcomings of high power consumption and low efficiency limit its application scenarios

For some dedicated neural network accelerators, the utilization rate of convolution computing resources is not high, and the configuration is complicated

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