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Three-dimensional semiconductor memory device

A semiconductor and memory technology, applied in the field of three-dimensional semiconductor memory devices, can solve problems such as expensive equipment and affecting integration

Active Publication Date: 2018-11-13
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In current two-dimensional or planar memory semiconductor devices, since the degree of integration is determined by the occupied area of ​​a unit memory cell, the technique for forming fine patterns considerably affects the degree of integration
However, in order to realize the formation of minute patterns, extremely expensive equipment is required

Method used

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Examples

Experimental program
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Embodiment Construction

[0022] figure 1 and image 3 is a diagram illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. image 3 is showing figure 1 Enlarged view of part A of .

[0023] refer to figure 1 and image 3 , the semiconductor substrate 100 includes a recessed region 102 . The recessed area 102 may extend in a horizontal direction. The active pattern 300 is disposed to extend in a direction transverse to the horizontal direction of the recessed region 102 . In one example, the active pattern 300 may vertically extend from the recessed region 102 .

[0024] In various embodiments, the semiconductor substrate 100 may be, for example, a silicon substrate, a germanium substrate, or a silicon germanium substrate. The active pattern 300 may be silicon, germanium or silicon germanium. The active pattern 300 may be formed of the same material as that of the semiconductor substrate 100 , such as silicon.

[0025] The lower select...

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PUM

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Abstract

The invention discloses a three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device includes a lower selection gate, a lower gate insulating layer and an activepattern; the lower selection gate is located on a semiconductor substrate; the lower gate insulating layer is located between the lower selection gate and the semiconductor substrate; and the active pattern extends in a direction perpendicular to the upper surface of the semiconductor substrate and penetrates the lower selection gate and lower gate insulating layer; and the lower surface of the lower gate insulating layer is lower than the upper surface of the semiconductor substrate.

Description

technical field [0001] The present disclosure herein relates to a semiconductor memory device, and more particularly, to a three-dimensional semiconductor memory device. Background technique [0002] Demands for further integration of semiconductor devices with superior performance and lower prices continue to increase. In semiconductor memory devices, since the degree of integration is an important factor in determining the resulting price, a higher degree of integration is particularly necessary. In current two-dimensional or planar memory semiconductor devices, since the degree of integration is determined by the occupied area of ​​a unit memory cell, techniques for forming fine patterns considerably affect the degree of integration. However, in order to realize the formation of minute patterns, extremely expensive equipment is required. [0003] Instead, techniques for forming three-dimensional memory cells continue to be developed. According to these techniques, sinc...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11556H01L27/11582H10B41/27H10B43/27
CPCH10B41/27H10B43/27
Inventor 金星中
Owner SAMSUNG ELECTRONICS CO LTD