Control method and device for convolutional neural network processor
A technology of convolutional neural network and control method, which is applied in the improvement field of hardware acceleration, can solve the problems that hardware utilization rate needs to be improved, and achieve the effect of improving multiplexing rate, reducing hardware computing units, and increasing utilization rate
Inactive Publication Date: 2018-11-23
INST OF COMPUTING TECH CHINESE ACAD OF SCI
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[0007] However, no matter which of the above existing techniques is used to design a convolutional neural network processor, there is still room for improvement in hardware utilization
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[0052] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0053] The inventor found in the process of researching the existing technology that various existing classical neural networks, such as Alexnet, GoogleNet, VGG, Resnet, etc., all contain different numbers of convolutional layers, and different convolutional layers The size of the convolution kernel used is also different. For example Alexnet, the first layer of the network is a convolutional layer with a convolution kernel size of 11*11, the second layer of the network is a convolutional layer with a convolution kernel size of 5*5, and the third layer of the network is a convolutional layer A convolutional layer with a kernel size of 3*3 and so on.
[0054] However, in various existing neural network processors, different computing units are set for convolution kernels of different sizes. As a result, when the calculation of a certain conv...
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The invention provides a control method, which comprises: 1) determining the size n*n of the convolution operation to be performed; 2) Selecting the value of the convolution kernel corresponding to the size to be loaded in m2 7*7 convolution calculation units, and filling the remaining values with 0. 7m is greater than or equal to n according to the size n*n of the convolution operation to be performed; 3) Determining the number of cycles required for the convolution calculation process according to the size of the convolution operation to be performed, the size of the input feature map to besubjected to convolution; 4) Loading the values of the corresponding input feature map into the m2 7*7 convolution calculation units in each cycle of the convolution calculation process, the distribution of the value of the input feature map in the m2 7*7 convolution calculation units is consistent with the distribution of the value of the convolution kernel in the m2 7*7 convolution calculation units; Controlling the m2 7*7 convolution calculation units loaded with convolution kernel and the values of the input feature map to respectively perform convolution calculation corresponding to the number of cycle.
Description
technical field [0001] The invention relates to a convolutional neural network processor, in particular to improvements in hardware acceleration for the convolutional neural network processor. Background technique [0002] Artificial intelligence technology has developed rapidly in recent years and has attracted widespread attention all over the world. Both industry and academia have carried out research work on artificial intelligence technology, infiltrating artificial intelligence technology into visual perception, Speech recognition, assisted driving, smart home, traffic dispatching and other fields. Deep learning technology is a booster for the development of artificial intelligence technology. Deep learning uses the topological structure of the deep neural network for training, optimization, and reasoning. The deep neural network white block convolutional neural network, deep belief network, and cyclic neural network, etc., undergo repeated iterations and training. T...
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IPC IPC(8): G06N3/063
CPCG06N3/063
Inventor 韩银和许浩博王颖
Owner INST OF COMPUTING TECH CHINESE ACAD OF SCI