Three-dimensional multi-core processor hybrid cache architecture and method

Abstract

The invention discloses a three-dimensional multi-core processor hybrid cache architecture and method. The hybrid cache architecture comprises a processor layer and a plurality of cache layers, wherein each node in the processor layer comprises a processor core and a private first-level instruction cache and a data cache, each node in each cache layer is a second-level shared cache bank, and an SRAM or STT-RAM is employed by each cache bank. The processor cores or the cache Banks of each layer are interconnected by routing, and the layers are connected by a TSV in the vertical direction. According to the architecture and method, the SRAM or STT-RAM storage media are used for the caches, the low delay when the processor cores frequently access a cache intermediate bank is ensured, the static power consumption of the overall cache is reduced, the migration of data between different banks is achieved, the data migration jitter of a multi-core processor is reduced, and the problem of a migration failure of a mixed cache data is solved.

Description

technical field [0001] The invention relates to a three-dimensional multi-core processor hybrid cache architecture and method, and belongs to the technical field of multi-core processors. Background technique [0002] As the scale of multi-core processors increases, the demand for on-chip cache capacity increases. The three-dimensional integrated circuit (Three-Dimensional Integrated Circuit, 3D IC) technology can stack multiple cache layers together, thereby increasing the capacity of the Cache in the entire chip. [0003] For large-capacity Cache, Non-Uniform Cache Architecture (NUCA) is often used. NUCA allows Cache Banks to have different access latencies, and D-NUCA is one of NUCAs. In D-NUCA, a hit counter is set for the Cache line. When the number of hits reaches the threshold, the data in the Cache line is migrated to a bank close to the processor, so as to shorten the delay for the processor to access the data next time. [0004] In the existing cache architectur...

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Problems solved by technology

[0007] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art, provide a three-dimensional multi-core processor hybrid cache architecture and method, and solve the problem of large static power consumption of the traditional multi-core processor cache, jittering phenomenon prone to data migration, and hybrid cache The problem of data migration failure

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