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Method and system for verifying address space of system-level chip

A system-level chip and address space technology, applied in memory systems, memory address/allocation/relocation, instruments, etc., can solve the problem of increasing the number of storage particles and storage particle capacity, increasing the complexity and cost of verification system design, etc.

Active Publication Date: 2018-12-11
LOONGSON TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This requires that in the system-level design, the storage interface needs to be equipped with corresponding size storage particles, that is, for a storage interface with multiple chip selection signals, the corresponding number of storage particles needs to be integrated on the board; and, for each chip selection, Each corresponding storage particle needs to support the same capacity as the storage interface. These two points correspondingly increase the requirements for the number of storage particles and the capacity of each storage particle, and increase the design complexity and cost of the verification system.

Method used

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  • Method and system for verifying address space of system-level chip
  • Method and system for verifying address space of system-level chip
  • Method and system for verifying address space of system-level chip

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Embodiment 1

[0042] A system-on-a-chip address space verification method provided by an embodiment of the present invention is introduced in detail.

[0043] refer to figure 1 , which shows a flow chart of the steps of a system-on-a-chip address space verification method in an embodiment of the present invention, which is applied to a system for verifying a system-on-a-chip 201. Refer to figure 2 In the verification system shown, the system includes an address decoding unit 202 and a storage particle 203, the address decoding unit 202 is respectively connected to the system-on-chip 201 and the storage particle 203, and the storage particle 203 is connected to the SoC 201;

[0044] The methods include:

[0045] Step 101, the address decoding unit equally divides the address space of the SoC according to the capacity of storage particles.

[0046] In this embodiment, the address decoding unit 202 equally divides the address space of the SoC 201 according to the capacity of the memory par...

Embodiment 2

[0059] refer to image 3 , which shows a flow chart of the steps of a system-on-a-chip address space verification method in an embodiment of the present invention, which is applied to an address space verification system connected to a system-on-a-chip 201. Refer to Figure 5 In the verification system shown, the system includes an address decoding unit 202 and a storage particle 203, and the address decoding unit 202 includes a first selection switch 2021, a decoder 2022, and a second selection switch 2023 connected in sequence.

[0060] The methods include:

[0061] Step 301, the first selection switch selects a chip-selected address space, and transmits the selected chip-selected address space to the decoder.

[0062] In this embodiment, the address space of the SoC 201 may include multiple chip-selected address spaces. For example, the address space of the SoC 201 is 128MB, and the address space of 128MB can be divided into 4 chip selects, each of which is 32MB, or the a...

Embodiment 3

[0079] A system-on-a-chip address space verification system provided by an embodiment of the present invention is introduced in detail.

[0080] refer to figure 2 , shows a schematic diagram of a system-on-chip address space verification system in an embodiment of the present invention.

[0081] The system includes an address decoding unit 202 and a storage particle 203;

[0082] The address space input port of the address decoding unit 202 is connected to the address space output port of the SoC 201, and the address space output port of the address decoding unit 202 is connected to the address space input port of the memory particle 203;

[0083] The read-write port of the storage particle 203 is connected to the read-write port of the system-on-chip 201, and the storage data transmission port of the storage particle 203 is connected to the storage data transmission port of the system-on-chip 201;

[0084] The address decoding unit 202 is configured to obtain the address s...

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Abstract

The invention provides a method and system for verifying an address space of a system-level chip. The method comprises the steps that: an address decoding unit divides the address space of the system-level chip into equal parts according to the capacity of a storage particle; the address decoding unit acquires an equally divided single address space until all address spaces of the system-level chip are obtained; the address decoding unit transmits a single address space acquired in each time to the storage particle; the storage particle receives a data reading and writing command sent by the system-level chip; the storage particle carries out data reading and writing verification on the single address space of the system-level chip transmitted by the address decoding unit until all the address spaces of the system-level chip are verified. Through the embodiment of the invention, the address space verification coverage rate of the system-level chip can achieve 100%, the capacity and quantity requirements of a system verification scheme for the storage particle are solved, the complexity of the system design is reduced, and the cost is saved.

Description

technical field [0001] The invention relates to the field of system-level chips, in particular to a system-level chip address space verification method and system. Background technique [0002] During the SOC (System-on-a-Chip, system-level) chip verification process, it often involves the verification of the address space on the storage interface, such as SRAM (Static RAM, static random access memory), LOCAL IO (LOCAL Input / Output, local input / output) interface, etc. In order to improve the verification coverage, the storage interface needs to be verified to every byte address. This requires that in the system-level design, the storage interface needs to be equipped with corresponding size storage particles, that is, for a storage interface with multiple chip selection signals, the corresponding number of storage particles needs to be integrated on the board; and, for each chip selection, Each corresponding storage particle needs to support the same capacity as the storag...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/06
CPCG06F12/0615
Inventor 吴少校
Owner LOONGSON TECH CORP