Electronic package and method for fabricating the same

Abstract

The present disclosure provides an electronic package and a method for fabricating the same. The method including: connecting a first carrier structure with an electronic component via a bonding layerformed thereon; stacking the first carrier structure on a second carrier structure via a plurality of conductive elements; and electrically connecting the electronic component to the second carrier structure to thereby maintain and secure the distance between the first and second carrier structures.

Description

technical field [0001] The present invention relates to a package structure, in particular to an electronic package and its manufacturing method. Background technique [0002] With the vigorous development of portable electronic products in recent years, various related products are gradually developing towards the trend of high density, high performance, light, thin, short and small. In response to this trend, the semiconductor packaging industry has developed various forms stacked package (package on package, referred to as PoP) technology, in order to meet the requirements of light, small and high density. [0003] like figure 1 As shown, in the existing stacked semiconductor package 1 manufacturing method, the semiconductor chip 11 is flip-chip bonded to a first packaging substrate 10 with a plurality of solder bumps 110, and the second step is performed after reflowing these solder bumps 110. After a flux cleaning operation, the primer 14 is used to cover the solder b...

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Problems solved by technology

[0004] However, in the existing semiconductor package 1, the distance between the first package substrate 10 and the second package substrate 12 is controlled by the conductive element 18, so the volume and height tolerance of the conductive element 18 after reflow is large. , not only the contacts are prone to defects, leading to poor electrical connection quality, but also the grid array (grid array) arranged by the conductive elements 18 is prone to poor coplanarity, resulting in unbalanced contact stress (stress) and easy This causes the first and second packaging substrates 10, 12 to be placed in an oblique manner, and even cause the problem of contact offset

[0005] Furthermore, the manufacturing process of the existing semiconductor package 1 is relatively complicated (for example, two flux cleaning operations are required) and the manufacturing cost is relatively high.

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